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DS32EV100 PDF预览

DS32EV100

更新时间: 2024-11-25 02:56:43
品牌 Logo 应用领域
美国国家半导体 - NSC 模拟传输接口电信集成电路电信电路
页数 文件大小 规格书
10页 636K
描述
Programmable Single Equalizer

DS32EV100 技术参数

生命周期:Transferred包装说明:HVSON,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.25Is Samacsys:N
JESD-30 代码:R-XDSO-N14长度:4 mm
功能数量:1端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
认证状态:Not Qualified座面最大高度:0.8 mm
标称供电电压:2.5 V表面贴装:YES
电信集成电路类型:LINE EQUALIZER温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL宽度:3 mm
Base Number Matches:1

DS32EV100 数据手册

 浏览型号DS32EV100的Datasheet PDF文件第2页浏览型号DS32EV100的Datasheet PDF文件第3页浏览型号DS32EV100的Datasheet PDF文件第4页浏览型号DS32EV100的Datasheet PDF文件第5页浏览型号DS32EV100的Datasheet PDF文件第6页浏览型号DS32EV100的Datasheet PDF文件第7页 
November 5, 2007  
DS32EV100  
Programmable Single Equalizer  
General Description  
Features  
The DS32EV100 programmable equalizer provides compen-  
sation for transmission medium losses and reduces the medi-  
um-induced deterministic jitter for NRZ data channel. The  
DS32EV100 is optimized for operation up to 3.2 Gbps for both  
cables and FR4 traces. The equalizer channel has eight lev-  
els of input equalization that can be programmed by three  
control pins.  
Equalizes up to 14 dB loss at 3.2 Gbps  
8 levels of programmable equalization  
Operates up to 3.2 Gbps with 40” FR4 traces  
0.12 UI residual deterministic jitter at 3.2 Gbps with 40”  
FR4 traces  
Single 2.5V or 3.3V power supply  
Supports AC or DC-Coupling with wide input common-  
mode  
The equalizer supports both AC and DC-coupled data paths  
for long run length data patterns such as PRBS-31, and bal-  
anced codes such as 8b/10b. The device uses differential  
current-mode logic (CML) inputs and outputs, and is available  
in a 3 mm x 4 mm 14-pin leadless LLP package. Power is  
supplied from either a 2.5V or 3.3V supply.  
Low power consumption: 100 mW Typ at 2.5V  
Small 3 mm x 4 mm 14-pin LLP package  
>8 kV HBM ESD  
-40 to 85°C operating temperature range  
Simplified Application Diagram  
20206501  
© 2007 National Semiconductor Corporation  
202065  
www.national.com  

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