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DS32ELX0124SQXE/NOPB PDF预览

DS32ELX0124SQXE/NOPB

更新时间: 2024-02-01 07:19:06
品牌 Logo 应用领域
德州仪器 - TI 驱动接口集成电路驱动器
页数 文件大小 规格书
31页 1468K
描述
DUAL LINE TRANSCEIVER, QCC48

DS32ELX0124SQXE/NOPB 技术参数

生命周期:Obsolete包装说明:LLP-48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.66
Is Samacsys:N差分输出:YES
驱动器位数:2接口集成电路类型:LINE TRANSCEIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-XQCC-N48
长度:7 mm功能数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:VQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, VERY THIN PROFILE接收器位数:2
座面最大高度:0.8 mm最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
电源电压1-最大:3.465 V电源电压1-分钟:3.135 V
电源电压1-Nom:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:7 mmBase Number Matches:1

DS32ELX0124SQXE/NOPB 数据手册

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DS32EL0124, DS32ELX0124  
125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel  
Interface  
General Description  
Features  
The DS32EL0124/DS32ELX0124 integrates clock and data  
recovery modules for high-speed serial communication over  
FR-4 printed circuit board backplanes, balanced cables, and  
optical fiber. This easy-to-use chipset integrates advanced  
signal and clock conditioning functions, with an FPGA friendly  
interface.  
5-bit DDR LVDS parallel data interface  
Programmable Receive Equalization  
Selectable DC-balance decoder  
Selectable De-scrambler  
Remote Sense for automatic detection and negotiation of  
link status  
The DS32EL0124/DS32ELX0124 deserializes up to 3.125  
Gbps of high speed serial data to 5 LVDS outputs without the  
need for an external reference clock. With DC-balance de-  
coding enabled, the application payload of 2.5 Gbps is dese-  
rialized to 4 LVDS outputs.  
No external receiver reference clock required  
LVDS parallel interface  
Programmable LVDS output clock delay  
Supports output data-valid signaling  
The DS32EL0124/DS32ELX01214 deserializers feature a re-  
mote sense capability to automatically signal link status con-  
ditions to its companion DS32EL0421/ELX0421 serializers  
without requiring an additional feedback path.  
Supports keep-alive clock output  
On chip LC VCOs  
Redundant serial input (ELX device only)  
The parallel LVDS interface of these devices reduce FPGA  
I/O pins, board trace count and alleviates EMI issues, when  
compared to traditional single-ended wide bus interfaces.  
Retimed serial output (ELX device only)  
Configurable PLL loop bandwidth  
Configurable via SMBus  
The DS32EL0124/ELX0124 is programmable through a SM-  
Bus interface as well as through control pins.  
Loss of lock and error reporting  
48-pin LLP package with exposed DAP  
Applications  
Key Specifications  
Imaging: Industrial, Medical Security, Printers  
1.25 to 3.125 Gbps serial data rate  
Displays: LED walls, Commercial  
125 to 312.5 MHz DDR parallel clock  
Video Transport  
-40° to +85°C temperature range  
Communication Systems  
> 8 kV ESD (HBM) protection  
Test and Measurement  
0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)  
Industrial Bus  
Typical Application  
PRODUCTION DATA information is current as of  
publication date. Products conform to specifications per  
the terms of the Texas Instruments standard warranty.  
Production processing does not necessarily include  
testing of all parameters.  
300431 SNLS284J  
Copyright © 1999-2012, Texas Instruments Incorporated  

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