June 1989
54LS109/DM54LS109A/DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is accepted by the flip-flop on the rising edge of the
clock pulse. The triggering occurs at a voltage level and is
not directly related to the transition time of the rising edge of
the clock. The data on the J and K inputs may be changed
while the clock is high or low as long as setup and hold
times are not violated. A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Features
Y
Alternate Military/Aerospace device (54LS109) is avail-
able. Contact a National Semiconductor Sales Office/
Distributor for specifications
Connection Diagram
Dual-In-Line Package
TL/F/6368–1
Order Number 54LS109DMQB, 54LS109FMQB, DM54LS109AJ,
DM54LS109AW, DM74LS109AM or DM74LS109AN
See NS Package Number J16A, M16A, N16E or W16A
Function Table
e
e
e
H
L
High Logic Level
Inputs
Outputs
Low Logic Level
PR
CLR
CLK
J
K
Q
Q
X
Either Low or High Logic Level
e
Rising Edge of Pulse
This configuration is nonstable; that is, it will not persist when preset
and/or clear inputs return to their inactive (high) state.
u
*
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
u
u
u
u
L
X
X
X
L
H
L
X
X
X
L
H
L
H*
L
L
H
H*
H
e
e
established.
Q
The output logic level of Q before the indicated input conditions were
0
L
Toggle
e
Toggle
each active transition of the clock pulse.
Each output changes to the complement of its previous level on
H
H
X
Q
0
H
Q
0
L
H
X
Q
Q
0
0
C
1995 National Semiconductor Corporation
TL/F/6368
RRD-B30M105/Printed in U. S. A.