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DM74LS10N PDF预览

DM74LS10N

更新时间: 2024-11-03 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
4页 49K
描述
Triple 3-Input NAND Gate

DM74LS10N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.3
系列:LSJESD-30 代码:R-PDIP-T14
JESD-609代码:e0长度:19.18 mm
逻辑集成电路类型:NAND GATE最大I(ol):0.008 A
功能数量:3输入次数:3
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):3.3 mAProp。Delay @ Nom-Sup:15 ns
传播延迟(tpd):15 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

DM74LS10N 数据手册

 浏览型号DM74LS10N的Datasheet PDF文件第2页浏览型号DM74LS10N的Datasheet PDF文件第3页浏览型号DM74LS10N的Datasheet PDF文件第4页 
August 1986  
Revised March 2000  
DM74LS10  
Triple 3-Input NAND Gate  
General Description  
This device contains three independent gates each of  
which performs the logic NAND function.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS10M  
DM74LS10N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = ABC  
Inputs  
Output  
A
X
X
L
B
X
L
C
L
Y
H
H
H
L
X
X
H
X
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
X = Either LOW or HIGH Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006349  
www.fairchildsemi.com  

DM74LS10N 替代型号

型号 品牌 替代类型 描述 数据表
SN74LS10N ONSEMI

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TRIPLE 3-INPUT NAND GATE
SN74LS10N TI

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TRIPLE 3-INPUT POSITIVE-NAND GATES
SN54S10J TI

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TRIPLE 3-INPUT POSITIVE-NAND GATES

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