是否Rohs认证: | 不符合 | 生命周期: | Obsolete |
零件包装代码: | DIP | 包装说明: | DIP, DIP14,.3 |
针数: | 14 | Reach Compliance Code: | unknown |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.3 |
系列: | LS | JESD-30 代码: | R-PDIP-T14 |
JESD-609代码: | e0 | 长度: | 19.18 mm |
逻辑集成电路类型: | NAND GATE | 最大I(ol): | 0.008 A |
功能数量: | 3 | 输入次数: | 3 |
端子数量: | 14 | 最高工作温度: | 70 °C |
最低工作温度: | 封装主体材料: | PLASTIC/EPOXY | |
封装代码: | DIP | 封装等效代码: | DIP14,.3 |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
峰值回流温度(摄氏度): | NOT SPECIFIED | 电源: | 5 V |
最大电源电流(ICC): | 3.3 mA | Prop。Delay @ Nom-Sup: | 15 ns |
传播延迟(tpd): | 15 ns | 认证状态: | Not Qualified |
施密特触发器: | NO | 座面最大高度: | 5.08 mm |
子类别: | Gates | 最大供电电压 (Vsup): | 5.25 V |
最小供电电压 (Vsup): | 4.75 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | NO | 技术: | TTL |
温度等级: | COMMERCIAL | 端子面层: | Tin/Lead (Sn/Pb) |
端子形式: | THROUGH-HOLE | 端子节距: | 2.54 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | NOT SPECIFIED |
宽度: | 7.62 mm | Base Number Matches: | 1 |
型号 | 品牌 | 替代类型 | 描述 | 数据表 |
SN74LS10N | ONSEMI |
类似代替 |
TRIPLE 3-INPUT NAND GATE | |
SN74LS10N | TI |
类似代替 |
TRIPLE 3-INPUT POSITIVE-NAND GATES | |
SN54S10J | TI |
类似代替 |
TRIPLE 3-INPUT POSITIVE-NAND GATES |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
DM74LS10N/A+ | ETC |
获取价格 |
Triple 3-input NAND Gate | |
DM74LS10N/B+ | ETC |
获取价格 |
Triple 3-input NAND Gate | |
DM74LS10W | NSC |
获取价格 |
Triple 3-Input NAND Gates | |
DM74LS11 | FAIRCHILD |
获取价格 |
Triple 3-Input AND Gate | |
DM74LS11 | NSC |
获取价格 |
Triple 3-Input AND Gates | |
DM74LS112A | FAIRCHILD |
获取价格 |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complement | |
DM74LS112A | NSC |
获取价格 |
DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENT | |
DM74LS112AM | NSC |
获取价格 |
DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENT | |
DM74LS112AMX | FAIRCHILD |
获取价格 |
J-K-Type Flip-Flop | |
DM74LS112AN | FAIRCHILD |
获取价格 |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complement |