Datasheet > DM54LS191

DM54LS191

更新时间： 2024-11-26 22:56:47

品牌	Logo	应用领域
美国国家半导体 - NSC		计数器
页数	文件大小	规格书
8页	168K
描述
Synchronous 4-Bit Up/Down Counters with Mode Control

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DM54LS191 数据手册

May 1989

DM54LS190/DM74LS190, DM54LS191/DM74LS191

Synchronous 4-Bit Up/Down Counters with Mode Control

General Description

These circuits are synchronous, reversible, up/down coun-

ters. The LS191 is a 4-bit binary counter and the LS190 is a

BCD counter. Synchronous operation is provided by having

all flip-flops clocked simultaneously, so that the outputs

change simultaneously when so instructed by the steering

logic. This mode of operation eliminates the output counting

spikes normally associated with asynchronous (ripple clock)

counters.

Two outputs have been made available to perform the cas-

cading function: ripple clock and maximum/minimum count.

The latter output produces a high-level output pulse with a

duration approximately equal to one complete cycle of the

clock when the counter overflows or underflows. The ripple

clock output produces a low-level output pulse equal in

width to the low-level portion of the clock input when an

overflow or underflow condition exists. The counters can be

easily cascaded by feeding the ripple clock output to the

enable input of the succeeding counter if parallel clocking is

used, or to the clock input if parallel enabling is used. The

maximum/minimum count output can be used to accom-

plish look-ahead for high-speed operation.

The outputs of the four master-slave flip-flops are triggered

on a low-to-high level transition of the clock input, if the

enable input is low. A high at the enable input inhibits count-

ing. Level changes at either the enable input or the down/

up input should be made only when the clock input is high.

The direction of the count is determined by the level of the

down/up input. When low, the counter counts up and when

high, it counts down.

Features

Counts 8-4-2-1 BCD or binary

Single down/up count control line

These counters are fully programmable; that is, the outputs

may be preset to either level by placing a low on the load

input and entering the desired data at the data inputs. The

output will change independent of the level of the clock in-

put. This feature allows the counters to be used as modulo-

N dividers by simply modifying the count length with the

preset inputs.

Count enable control input

Ripple clock output for cascading

Asynchronously presettable with load control

Parallel outputs

Cascadable for n-bit applications

Average propagation delay 20 ns

The clock, down/up, and load inputs are buffered to lower

the drive requirement; which significantly reduces the num-

ber of clock drivers, etc., required for long parallel words.

Typical clock frequency 25 MHz

Typical power dissipation 100 mW

Connection Diagram

Dual-In-Line-Package

TL/F/6405-1

Order Number DM54LS190J, DM54LS191J, DM54LS190W,

DM54LS191W, DM74LS190M, DM74LS191M, DM74LS190N, or DM74LS191N

See NS Package Number

J16A, M16A, N16A or W16A

1995 National Semiconductor Corporation

TL/F/6405

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7 8

中文翻译

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与DM54LS191相关器件

型号	品牌	获取价格	描述	数据表
DM54LS191J	NSC	获取价格	Synchronous 4-Bit Up/Down Counters with Mode Control
DM54LS191J	FAIRCHILD	获取价格	Binary Counter, Synchronous, Bidirectional, TTL, CDIP16,
DM54LS191J/883	TI	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDIP16, CERAMIC
DM54LS191J/883B	TI	获取价格	IC,COUNTER,UP/DOWN,4-BIT BINARY,LS-TTL,DIP,16PIN,CERAMIC
DM54LS191J/883C	TI	获取价格	IC,COUNTER,UP/DOWN,4-BIT BINARY,LS-TTL,DIP,16PIN,CERAMIC
DM54LS191W	NSC	获取价格	Synchronous 4-Bit Up/Down Counters with Mode Control
DM54LS191W/883	TI	获取价格	IC LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDFP16, W16A
DM54LS191W/883B	TI	获取价格	IC,COUNTER,UP/DOWN,4-BIT BINARY,LS-TTL,FP,16PIN,CERAMIC
DM54LS193E/883	ETC	获取价格	Synchronous Up/Down Counter
DM54LS193J	ETC	获取价格	Synchronous Up/Down Counter

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