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DM54LS191J PDF预览

DM54LS191J

更新时间: 2024-01-17 21:24:16
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器
页数 文件大小 规格书
8页 168K
描述
Synchronous 4-Bit Up/Down Counters with Mode Control

DM54LS191J 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:DFP, FL16,.3Reach Compliance Code:unknown
风险等级:5.84计数方向:BIDIRECTIONAL
JESD-30 代码:R-XDFP-F16JESD-609代码:e0
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:20000000 Hz最大I(ol):0.004 A
工作模式:SYNCHRONOUS功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC
封装代码:DFP封装等效代码:FL16,.3
封装形状:RECTANGULAR封装形式:FLATPACK
电源:5 V最大电源电流(ICC):35 mA
认证状态:Not Qualified子类别:Counters
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

DM54LS191J 数据手册

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May 1989  
DM54LS190/DM74LS190, DM54LS191/DM74LS191  
Synchronous 4-Bit Up/Down Counters with Mode Control  
General Description  
These circuits are synchronous, reversible, up/down coun-  
ters. The LS191 is a 4-bit binary counter and the LS190 is a  
BCD counter. Synchronous operation is provided by having  
all flip-flops clocked simultaneously, so that the outputs  
change simultaneously when so instructed by the steering  
logic. This mode of operation eliminates the output counting  
spikes normally associated with asynchronous (ripple clock)  
counters.  
Two outputs have been made available to perform the cas-  
cading function: ripple clock and maximum/minimum count.  
The latter output produces a high-level output pulse with a  
duration approximately equal to one complete cycle of the  
clock when the counter overflows or underflows. The ripple  
clock output produces a low-level output pulse equal in  
width to the low-level portion of the clock input when an  
overflow or underflow condition exists. The counters can be  
easily cascaded by feeding the ripple clock output to the  
enable input of the succeeding counter if parallel clocking is  
used, or to the clock input if parallel enabling is used. The  
maximum/minimum count output can be used to accom-  
plish look-ahead for high-speed operation.  
The outputs of the four master-slave flip-flops are triggered  
on a low-to-high level transition of the clock input, if the  
enable input is low. A high at the enable input inhibits count-  
ing. Level changes at either the enable input or the down/  
up input should be made only when the clock input is high.  
The direction of the count is determined by the level of the  
down/up input. When low, the counter counts up and when  
high, it counts down.  
Features  
Y
Counts 8-4-2-1 BCD or binary  
Y
Single down/up count control line  
These counters are fully programmable; that is, the outputs  
may be preset to either level by placing a low on the load  
input and entering the desired data at the data inputs. The  
output will change independent of the level of the clock in-  
put. This feature allows the counters to be used as modulo-  
N dividers by simply modifying the count length with the  
preset inputs.  
Y
Count enable control input  
Y
Ripple clock output for cascading  
Y
Asynchronously presettable with load control  
Y
Parallel outputs  
Y
Cascadable for n-bit applications  
Y
Average propagation delay 20 ns  
The clock, down/up, and load inputs are buffered to lower  
the drive requirement; which significantly reduces the num-  
ber of clock drivers, etc., required for long parallel words.  
Y
Typical clock frequency 25 MHz  
Y
Typical power dissipation 100 mW  
Connection Diagram  
Dual-In-Line-Package  
TL/F/6405-1  
Order Number DM54LS190J, DM54LS191J, DM54LS190W,  
DM54LS191W, DM74LS190M, DM74LS191M, DM74LS190N, or DM74LS191N  
See NS Package Number  
J16A, M16A, N16A or W16A  
C
1995 National Semiconductor Corporation  
TL/F/6405  
RRD-B30M105/Printed in U. S. A.  

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