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DM54LS107AW PDF预览

DM54LS107AW

更新时间: 2024-09-15 22:56:47
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
6页 122K
描述
Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

DM54LS107AW 数据手册

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June 1989  
DM54LS107A/DM74LS107A Dual Negative-Edge-  
Triggered Master-Slave J-K Flip-Flops with  
Clear and Complementary Outputs  
General Description  
This device contains two independent negative-edge-trig-  
gered J-K flip-flops with complementary outputs. The J and  
K data is processed by the flip-flops on the falling edge of  
the clock pulse. The clock triggering occurs at a voltage  
level and is not directly related to the transition time of the  
negative going edge of the clock pulse. The data on the J  
and K inputs may change while the clock is high or low  
without affecting the outputs as long as setup and hold  
times are not violated. A low logic level on the clear input  
will reset the outputs regardless of the logic levels of the  
other inputs.  
Connection Diagram  
Dual-In-Line Package  
TL/F/6367–1  
Order Number DM54LS107AJ, DM54LS107AW, DM74LS107AM or DM74LS107AN  
See NS Package Number J14A, M14A, N14A or W14B  
Function Table  
Inputs  
CLK  
Outputs  
CLR  
J
K
Q
Q
L
X
X
L
X
L
L
H
H
H
H
H
H
Q
0
Q
0
v
v
v
v
H
H
L
L
H
L
L
H
H
X
H
H
X
Toggle  
Q
0
Q
0
e
H
X
L
High Logic Level  
e
e
Either Low or High Logic Level  
Low Logic Level  
e
Negative going edge of pulse.  
v
0
e
Q
The output logic level before the indicated input conditions were established.  
e
Toggle  
Each output changes to the complement of its previous level on each falling edge of the clock pulse.  
C
1995 National Semiconductor Corporation  
TL/F/6367  
RRD-B30M105/Printed in U. S. A.  

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