DM54LS109A

更新时间： 2024-09-15 22:56:47

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器
页数	文件大小	规格书
6页	137K
描述
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

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DM54LS109A 数据手册

June 1989

54LS109/DM54LS109A/DM74LS109A

Dual Positive-Edge-Triggered J-K Flip-Flops

with Preset, Clear, and Complementary Outputs

General Description

This device contains two independent positive-edge-trig-

gered J-K flip-flops with complementary outputs. The J and

K data is accepted by the flip-flop on the rising edge of the

clock pulse. The triggering occurs at a voltage level and is

not directly related to the transition time of the rising edge of

the clock. The data on the J and K inputs may be changed

while the clock is high or low as long as setup and hold

times are not violated. A low logic level on the preset or

clear inputs will set or reset the outputs regardless of the

logic levels of the other inputs.

Features

Alternate Military/Aerospace device (54LS109) is avail-

able. Contact a National Semiconductor Sales Office/

Distributor for specifications

Connection Diagram

Dual-In-Line Package

TL/F/6368–1

Order Number 54LS109DMQB, 54LS109FMQB, DM54LS109AJ,

DM54LS109AW, DM74LS109AM or DM74LS109AN

See NS Package Number J16A, M16A, N16E or W16A

Function Table

High Logic Level

Inputs

Outputs

Low Logic Level

CLR

CLK

Either Low or High Logic Level

Rising Edge of Pulse

This configuration is nonstable; that is, it will not persist when preset

and/or clear inputs return to their inactive (high) state.

established.

The output logic level of Q before the indicated input conditions were

Toggle

each active transition of the clock pulse.

Each output changes to the complement of its previous level on

1995 National Semiconductor Corporation

TL/F/6368

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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DM54LS109AM	NSC	获取价格	Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs
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