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CYD18S72V-100BBI PDF预览

CYD18S72V-100BBI

更新时间： 2024-11-06 22:21:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
26页 470K
描述
FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM

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中文翻译

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CYD18S72V-100BBI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：23 X 23 MM, 1 MM, MO-192, FBGA-484针数：484
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.48
最长访问时间：5.2 ns其他特性：PIPELINED ARCHITECTURE OR FLOW-THROUGH
最大时钟频率 (fCLK)：100 MHzI/O 类型：COMMON
JESD-30 代码：S-PBGA-B484JESD-609代码：e0
长度：23 mm内存密度：18874368 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：72
湿度敏感等级：3功能数量：1
端口数量：2端子数量：484
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX72
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA484,22X22,40
封装形状：SQUARE封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：220
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.9 mm最大待机电流：0.075 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.45 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：23 mmBase Number Matches：1

CYD18S72V-100BBI 数据手册

 浏览型号CYD18S72V-100BBI的Datasheet PDF文件第2页浏览型号CYD18S72V-100BBI的Datasheet PDF文件第3页浏览型号CYD18S72V-100BBI的Datasheet PDF文件第4页浏览型号CYD18S72V-100BBI的Datasheet PDF文件第5页浏览型号CYD18S72V-100BBI的Datasheet PDF文件第6页浏览型号CYD18S72V-100BBI的Datasheet PDF文件第7页 
CYD04S72V  
CYD09S72V  
CYD18S72V  
PRELIMINARY  
FLEx72™ 3.3V 64K/128K/256K x 72  
Synchronous Dual-Port RAM  
Functional Description  
Features  
• True dual-ported memory cells that allow simultaneous  
The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit  
pipelined, synchronous, true dual-port static RAMs that are  
high-speed, low-power 3.3V CMOS. Two ports are provided,  
permitting independent, simultaneous access to any location  
in memory. The result of writing to the same location by more  
than one port at the same time is undefined. Registers on  
control, address, and data lines allow for minimal set-up and  
hold time.  
During a Read operation, data is registered for decreased  
cycle time. Each port contains a burst counter on the input  
address register. After externally loading the counter with the  
initial address, the counter will increment the address inter-  
nally (more details to follow). The internal write pulse width is  
independent of the duration of the R/W input signal. The  
internal write pulse is self-timed to allow the shortest possible  
cycle times.  
A HIGH on CE0 or LOW on CE1 for one clock cycle will power  
down the internal circuitry to reduce the static power  
consumption. One cycle with chip enables asserted is required  
to reactivate the outputs.  
Additional features include: readback of burst-counter internal  
address value on address lines, counter-mask registers to  
control the counter wrap-around, counter interrupt (CNTINT)  
flags, readback of mask register value on address lines,  
retransmit functionality, interrupt flags for message passing,  
JTAG for boundary scan, and asynchronous Master Reset  
(MRST).  
access of the same memory location  
• Synchronous pipelined operation  
• Family of 4-Mbit, 9-Mbit and 18-Mbit devices  
• Pipelined output mode allows fast operation  
• 0.18-micron CMOS for optimum speed and power  
• High-speed clock to data access  
• 3.3V low power  
—Active as low as 225 mA (typ)  
— Standby as low as 55 mA (typ)  
• Mailbox function for message passing  
• Global master reset  
• Separate byte enables on both ports  
• Commercial and industrial temperature ranges  
• IEEE 1149.1-compatible JTAG boundary scan  
• 484-ball FBGA (1 mm pitch)  
• Counter wrap around control  
— Internal mask register controls counter wrap-around  
— Counter-interrupt flags to indicate wrap-around  
— Memory block retransmit operation  
• Counter readback on address lines  
• Mask register readback on address lines  
• Dual Chip Enables on both ports for easy depth  
expansion  
The CYD18S72V device have limited features. Please see  
“Address Counter and Mask Register Operations[16]” on  
page 6 for details.  
• Seamless Migration to Next Generation Dual Port  
Family  
Seamless Migration to Next Generation Dual Port Family  
Cypress offers a migration path for all devices to the  
next-generation devices in the Dual-Port family with a  
compatible footprint. Please contact Cypress Sales for more  
details  
Table 1. Product Selection Guide  
Density  
4-Mbit  
9-Mbit  
18-Mbit  
(64K x 72)  
CYD04S72V  
167  
(128K x 72)  
(256K x 72)  
Part Number  
Max. Speed (MHz)  
Max. Access Time - clock to Data (ns)  
Typical operating current (mA)  
Package  
CYD09S72V  
CYD18S72V  
167  
4.0  
270  
133  
5.0  
410  
4.0  
225  
484-ball FBGA  
484-ball FBGA  
484-ball FBGA  
23mm x 23mm  
23mm x 23mm  
23mm x 23mm  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-06069 Rev. *D  
Revised June 23, 2004  
1234567...26

中文翻译

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CYD18S72V-100BBI 替代型号

型号 品牌 替代类型 描述 数据表
CYD18S72V18-200BGXI CYPRESS

类似代替

 FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD18S72V18-167BGI CYPRESS

类似代替

 FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD18S72V-133BBI CYPRESS

类似代替

 FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous D

与CYD18S72V-100BBI相关器件

型号 品牌 获取价格 描述 数据表
CYD18S72V-100BBXC CYPRESS

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 		FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous D
CYD18S72V-100BBXI CYPRESS

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 		FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous D
CYD18S72V-133BBC CYPRESS

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 		FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
CYD18S72V-133BBI CYPRESS

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 		FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous D
CYD18S72V-133BBXC CYPRESS

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 		FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous D
CYD18S72V18 CYPRESS

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 		FullFlex Synchronous SDR Dual Port SRAM
CYD18S72V18-167BBC CYPRESS

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 		Dual-Port SRAM, 256KX72, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLAST
CYD18S72V18-167BBXC CYPRESS

获取价格

 		Dual-Port SRAM, 256KX72, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD
CYD18S72V18-167BBXI ROCHESTER

获取价格

 		256KX72 DUAL-PORT SRAM, 4ns, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD FREE, P
CYD18S72V18-167BBXI CYPRESS

获取价格

 		Dual-Port SRAM, 256KX72, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD

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