Datasheet > CYD18S72V18-167BBC

CYD18S72V18-167BBC

更新时间： 2024-11-08 07:35:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
48页	938K
描述
Dual-Port SRAM, 256KX72, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484

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PRELIMINARY

FullFlex™ Synchronous

SDR Dual-Port SRAM

— Selectable LVTTL (3.3V), Extended HSTL

(1.4V–1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on

each port

Features

• True dual-ported memory allows simultaneous access

to the shared array from each port

— Burst counters for sequential memory access

— Mailbox with interrupt flags for message passing

— Dual Chip Enables for easy depth expansion

• Synchronous pipelined operation with SDR operation

on each port

— Single Data Rate (SDR) interface at 250 MHz

— Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports)

• Selectable pipeline or flow-through mode

• Selectable 1.5V or 1.8V core power supply

• Commercial and Industrial temperature

• IEEE 1149.1 JTAG boundary scan

Functional Description

The FullFlex™ Dual-Port SRAM families consist of 4-Mbit,

9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static

RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two

ports are provided, allowing the array to be accessed simulta-

neously. Simultaneous access to a location triggers determin-

istic access control. For FullFlex72 these ports can operate

independently with 72-bit bus widths and each port can be

independently configured for two pipeline stages. Each port

can also be configured to operate in pipeline or flow-through

mode.

Advanced features include built-in deterministic access

control to manage address collisions during simultaneous

access to the same memory location, variable impedance

matching (VIM) to improve data transmission by matching the

output driver impedance to the line impedance, and echo

clocks to improve data transfer.

• Available in 484-ball PBGA Packages and 256-ball

FBGA packages

• FullFlex72 family

— 36-Mbit: 512K x 72 (CYD36S72V18)

— 18-Mbit: 256K x 72 (CYD18S72V18)

— 9-Mbit: 128K x 72 (CYD09S72V18)

— 4-Mbit: 64K x 72 (CYD04S72V18)

• FullFlex36 family

— 36-Mbit: 1M x 36 (CYD36S36V18)

— 18-Mbit: 512K x 36 (CYD18S36V18)

— 9-Mbit: 256K x 36 (CYD09S36V18)

— 4-Mbit: 128K x 36 (CYD04S36V18)

• FullFlex18 family

To reduce the static power consumption, chip enables can be

used to power down the internal circuitry. The number of

cycles of latency before a change in CE0 or CE1 will enable

or disable the databus matches the number of cycles of read

latency selected for the device. In order for a valid write or read

to occur, both chip enable inputs on a port must be active.

— 36-Mbit: 2M x 18 (CYD36S18V18)

— 18-Mbit: 1M x 18 (CYD18S18V18)

— 9-Mbit: 512K x 18 (CYD09S18V18)

— 4-Mbit: 256K x 18 (CYD04S18V18)

Each port contains an optional burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally.

Additional features of this device include a mask register and

• Built-in deterministic access control to manage

a mirror register to control counter increments and

address collisions

wrap-around, counter-interrupt (CNTINT) flags to notify that

the counter will reach the maximum value on the next clock

cycle, readback of the burst-counter internal address, mask

retransmit functionality, mailbox interrupt flags for message

passing, JTAG for boundary scan, and asynchronous Master

Reset (MRST). The logic block diagram in Figure 1 displays

these features.

— Deterministic flag output upon collision detection

— Collision detection on back-to-back clock cycles

— First Busy Address readback

• Advanced features for improved high-speed data

transfer and flexibility

— Variable Impedance Matching (VIM)

— Echo clocks

The FullFlex72 is offered in a 484-ball plastic BGA package.

The FullFlex36 and FullFlex18 are offered in a 256-ball fine

pitch BGA package.

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document #: 38-06082 Rev. *C

Revised October 11, 2005

12 3 4 5 6 7...48

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与CYD18S72V18-167BBC相关器件

型号	品牌	获取价格	描述	数据表
CYD18S72V18-167BBXC	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD
CYD18S72V18-167BBXI	ROCHESTER	获取价格	256KX72 DUAL-PORT SRAM, 4ns, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD FREE, P
CYD18S72V18-167BBXI	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD
CYD18S72V18-167BGC	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD18S72V18-167BGC	ROCHESTER	获取价格	256KX72 DUAL-PORT SRAM, 4ns, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA
CYD18S72V18-167BGI	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD18S72V18-167BGI	ROCHESTER	获取价格	256KX72 DUAL-PORT SRAM, 4ns, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA
CYD18S72V18-167BGXC	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD18S72V18-167BGXI	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 11ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD
CYD18S72V18-200BBC	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 3.3ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLA

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