Datasheet > CYD18S72V18-167BGXI

CYD18S72V18-167BGXI

更新时间： 2024-11-28 06:01:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
52页	1093K
描述
Dual-Port SRAM, 256KX72, 11ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-484

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FullFlex

FullFlex™ Synchronous SDR Dual Port SRAM

Features

Functional Description

■ True dual port memory enables simultaneous access to the

shared array from each port

The FullFlex™ dual port SRAM families consist of 2 Mbit, 4 Mbit,

9 Mbit, 18 Mbit, and 36 Mbit synchronous, true dual port static

RAMs that are high speed, low power 1.8V or 1.5V CMOS. Two

ports are provided, enabling simultaneous access to the array.

Simultaneous access to a location triggers deterministic access

control. For FullFlex72 these ports operate independently with

72-bit bus widths and each port is independently configured for

two pipelined stages. Each port is also configured to operate in

pipelined or flow through mode.

■ Synchronous pipelined operation with Single Data Rate (SDR)

operation on each port

❐ SDR interface at 200 MHz

❐ Up to 28.8 Gb/s bandwidth (200 MHz x 72 bit x 2 ports)

■ Selectable pipelined or flow-through mode

■ 1.5V or 1.8V core power supply

The advanced features include the following:

■ Commercial and Industrial temperature

■ IEEE 1149.1 JTAG boundary scan

■ Built in deterministic access control to manage address colli-

sions during simultaneous access tothesamememorylocation

■ Variable Impedance Matching (VIM) to improve data trans-

mission by matching the output driver impedance to the line

impedance

■ Available in 484-Ball PBGA (x72) and 256-Ball FBGA (x36 and

x18) packages

■ FullFlex72 family

■ Echo clocks to improve data transfer

❐ 36 Mbit: 512K x 72 (CYD36S72V18)

❐ 18 Mbit: 256K x 72 (CYD18S72V18)

❐ 9 Mbit: 128K x 72 (CYD09S72V18)

❐ 4 Mbit: 64K x 72 (CYD04S72V18)

To reduce the static power consumption, chip enables power

down the internal circuitry. The number of latency cycles before

a change in CE0 or CE1 enables or disables the databus

matches the number of cycles of read latency selected for the

device. For a valid write or read to occur, activate both chip

enable inputs on a port.

■ FullFlex36 family

❐ 36 Mbit: 1M x 36 (CYD36S36V18)

❐ 18 Mbit: 512K x 36 (CYD18S36V18)

❐ 9 Mbit: 256K x 36 (CYD09S36V18)

❐ 4 Mbit: 128K x 36 (CYD04S36V18)

❐ 2 Mbit: 64K x 36 (CYD02S36V18)

Each port contains an optional burst counter on the input address

address, the counter increments the address internally.

Additional device features include a mask register and a mirror

counter interrupt (CNTINT) flags notify the host that the counter

reaches maximum count value on the next clock cycle. The host

reads the burst counter internal address, mask register address,

and busy address on the address lines. The host also loads the

counter with the address stored in the mirror register by using the

retransmit functionality. Mailbox interrupt flags are used for

message passing, and JTAG boundary scan and asynchronous

Master Reset (MRST) are also available. The Logic Block

Diagram on page 2 shows these features.

■ FullFlex18 family

❐ 36 Mbit: 2M x 18 (CYD36S18V18)

❐ 18 Mbit: 1M x 18 (CYD18S18V18)

❐ 9 Mbit: 512K x 18 (CYD09S18V18)

❐ 4 Mbit: 256K x 18 (CYD04S18V18)

■ Built in deterministic access control to manage address colli-

sions

❐ Deterministic flag output upon collision detection

❐ Collision detection on back-to-back clock cycles

❐ First Busy Address readback

The FullFlex72 is offered in a 484-Ball plastic BGA package. The

FullFlex36 and FullFlex18 are available in 256-Ball fine pitch

BGA package.

■ Advanced features for improved high speed data transfer and

flexibility

❐ Variable Impedance Matching (VIM)

❐ Echo clocks

❐ Selectable LVTTL (3.3V), Extended HSTL (1.4V–1.9V), 1.8V

LVCMOS, or 2.5V LVCMOS IO on each port

❐ Burst counters for sequential memory access

❐ Mailbox with interrupt flags for message passing

❐ Dual Chip Enables for easy depth expansion

Cypress Semiconductor Corporation

Document Number: 38-06082 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 15, 2008

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与CYD18S72V18-167BGXI相关器件

型号	品牌	获取价格	描述	数据表
CYD18S72V18-200BBC	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 3.3ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLA
CYD18S72V18-200BBXC	CYPRESS	获取价格	暂无描述
CYD18S72V18-200BBXI	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 3.3ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEA
CYD18S72V18-200BGI	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD18S72V18-200BGI	ROCHESTER	获取价格	256KX72 DUAL-PORT SRAM, 3.3ns, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, B
CYD18S72V18-200BGXC	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 9ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD
CYD18S72V18-200BGXI	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD18S72V18-250BBXC	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 2.64ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LE
CYD36S18V18	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM
CYD36S18V18-133BBC	CYPRESS	获取价格	Dual-Port SRAM, 2MX18, 4.5ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLAST

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