Datasheet > 存储 > SRAM> CYD18S72V18-167BGC

CYD18S72V18-167BGC

更新时间： 2024-11-07 09:46:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
52页	1327K
描述
FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature

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CYD18S72V18-167BGC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484	针数：	484
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.81
最长访问时间：	4 ns	其他特性：	PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATES AT 1.8V
最大时钟频率 (fCLK)：	167 MHz	I/O 类型：	COMMON
JESD-30 代码：	S-PBGA-B484	JESD-609代码：	e0
长度：	23 mm	内存密度：	18874368 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	72
湿度敏感等级：	3	功能数量：	1
端口数量：	2	端子数量：	484
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	256KX72
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA484,22X22,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	1.5/1.8 V	认证状态：	Not Qualified
座面最大高度：	2.16 mm	最大待机电流：	0.3 A
最小待机电流：	1.4 V	子类别：	SRAMs
最大压摆率：	0.88 mA	最大供电电压 (Vsup)：	1.58 V
最小供电电压 (Vsup)：	1.42 V	标称供电电压 (Vsup)：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	23 mm	Base Number Matches：	1

CYD18S72V18-167BGC 数据手册

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FullFlex

FullFlex^TMSynchronous SDR

Dual Port SRAM

FullFlex^™Synchronous SDR Dual Port SRAM

Features

Functional Description

■ True dual port memory enables simultaneous access to the

shared array from each port

The FullFlex™ dual port SRAM families consist of 2-Mbit, 9-Mbit,

18-Mbit, and 36-Mbit synchronous, true dual port static RAMs

that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports

are provided, enabling simultaneous access to the array.

Simultaneous access to a location triggers deterministic access

control. For FullFlex72 these ports operate independently with

72-bit bus widths and each port is independently configured for

two pipelined stages. Each port is also configured to operate in

pipelined or flow through mode.

■ Synchronous pipelined operation with single data rate (SDR)

operation on each port

❐ SDR interface at 200 MHz

❐ Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)

■ Selectable pipelined or flow-through mode

■ 1.5 V or 1.8 V core power supply

The advanced features include the following:

■ Commercial and Industrial temperature

■ IEEE 1149.1 JTAG boundary scan

■ Built in deterministic access control to manage address

collisions during simultaneous access to the same memory

location

■ Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36

and × 18) packages

■ Variable Impedance Matching (VIM) to improve data

transmission by matching the output driver impedance to the

line impedance

■ FullFlex72 family

❐ 36-Mbit: 512 K × 72 (CYD36S72V18)

❐ 18-Mbit: 256 K × 72 (CYD18S72V18)

❐ 9-Mbit: 128 K × 72 (CYD09S72V18)

■ Echo clocks to improve data transfer

To reduce the static power consumption, chip enables power

down the internal circuitry. The number of latency cycles before

a change in CE0 or CE1 enables or disables the databus

matches the number of cycles of read latency selected for the

device. For a valid write or read to occur, activate both chip

enable inputs on a port.

■ FullFlex36 family

❐ 36-Mbit: 1 M × 36 (CYD36S36V18)

❐ 18-Mbit: 512 K × 36 (CYD18S36V18)

❐ 9-Mbit: 256 K × 36 (CYD09S36V18)

❐ 2-Mbit: 64 K × 36 (CYD02S36V18)

Each port contains an optional burst counter on the input address

address, the counter increments the address internally.

■ FullFlex18 family

❐ 36-Mbit: 2 M × 18 (CYD36S18V18)

❐ 18-Mbit: 1 M × 18 (CYD18S18V18)

❐ 9-Mbit: 512 K × 18 (CYD09S18V18)

Additional device features include a mask register and a mirror

counter interrupt (CNTINT) flags notify the host that the counter

reaches maximum count value on the next clock cycle. The host

reads the burst counter internal address, mask register address,

and busy address on the address lines. The host also loads the

counter with the address stored in the mirror register by using the

retransmit functionality. Mailbox interrupt flags are used for

message passing, and JTAG boundary scan and asynchronous

Master Reset (MRST) are also available. The Logic Block

Diagram on page 2 shows these features.

■ Built in deterministic access control to manage address

collisions

❐ Deterministic flag output upon collision detection

❐ Collision detection on back-to-back clock cycles

❐ First busy address readback

■ Advanced features for improved high speed data transfer and

flexibility

❐ Variable impedance matching (VIM)

❐ Echo clocks

❐ Selectable LVTTL (3.3 V), Extended HSTL (1.4 V to 1.9 V),

1.8 V LVCMOS, or 2.5 V LVCMOS IO on each port

❐ Burst counters for sequential memory access

❐ Mailbox with interrupt flags for message passing

❐ Dual chip enables for easy depth expansion

The FullFlex72 is offered in a 484-ball plastic BGA package. The

FullFlex36 and FullFlex18 are available in 256-ball fine pitch

BGA package except the 36-Mbit devices which are offered in

484-ball plastic BGA package.

Cypress Semiconductor Corporation

Document Number: 38-06082 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 31, 2011

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与CYD18S72V18-167BGC相关器件

型号	品牌	获取价格	描述	数据表
CYD18S72V18-167BGI	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD18S72V18-167BGI	ROCHESTER	获取价格	256KX72 DUAL-PORT SRAM, 4ns, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA
CYD18S72V18-167BGXC	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD18S72V18-167BGXI	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 11ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD
CYD18S72V18-200BBC	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 3.3ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLA
CYD18S72V18-200BBXC	CYPRESS	获取价格	暂无描述
CYD18S72V18-200BBXI	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 3.3ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEA
CYD18S72V18-200BGI	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD18S72V18-200BGI	ROCHESTER	获取价格	256KX72 DUAL-PORT SRAM, 3.3ns, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, B
CYD18S72V18-200BGXC	CYPRESS	获取价格	Dual-Port SRAM, 256KX72, 9ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD

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