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CY8C24094-24BVXIT PDF预览

CY8C24094-24BVXIT

更新时间: 2024-11-24 20:03:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟微控制器
页数 文件大小 规格书
72页 1149K
描述
Multifunction Peripheral, CMOS, PBGA100, 6 X 6 MM, LEAD FREE, MO-195C, VFBGA-100

CY8C24094-24BVXIT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:VFBGA, BGA100,10X10,20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.76
位大小:8边界扫描:NO
总线兼容性:I2C; USBCPU系列:M8C
最大时钟频率:24.06 MHzJESD-30 代码:S-PBGA-B100
JESD-609代码:e3长度:6 mm
湿度敏感等级:1I/O 线路数量:56
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装等效代码:BGA100,10X10,20
封装形状:SQUARE封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):225电源:3.3/5 V
认证状态:Not QualifiedRAM(字节):1024
RAM(字数):512ROM(单词):16384
ROM可编程性:FLASH座面最大高度:1 mm
速度:24 MHz子类别:Microcontrollers
最大压摆率:27 mA最大供电电压:5.25 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:BALL端子节距:0.5 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6 mmBase Number Matches:1

CY8C24094-24BVXIT 数据手册

 浏览型号CY8C24094-24BVXIT的Datasheet PDF文件第2页浏览型号CY8C24094-24BVXIT的Datasheet PDF文件第3页浏览型号CY8C24094-24BVXIT的Datasheet PDF文件第4页浏览型号CY8C24094-24BVXIT的Datasheet PDF文件第5页浏览型号CY8C24094-24BVXIT的Datasheet PDF文件第6页浏览型号CY8C24094-24BVXIT的Datasheet PDF文件第7页 
CY8C24094/CY8C24794  
CY8C24894/CY8C24994  
PSoC® Programmable System-on-Chip™  
PSoC® Programmable System-on-Chip™  
Up to 48 analog inputs on GPIOs  
Two 33 mA analog outputs on GPIOs  
Features  
XRES pin to support in-system serial programming (ISSP) and  
external reset control in CY8C24894  
Configurable interrupt on all GPIOs  
Precision, programmable clocking  
Powerful Harvard-architecture processor  
M8C processor speeds up to 24 MHz  
Two 8 × 8 multiply, 32-bit accumulate  
Low power at high speed  
Operating voltage: 3 V to 5.25 V  
Industrial temperature range: –40 °C to +85 °C  
USB temperature range: –10 °C to +85 °C  
Internal ±4% 24- / 48-MHz main oscillator  
Internal oscillator for watchdog and sleep  
0.25% accuracy for USB with no external components  
Additional system resources  
I2C slave, master, and multi-master to 400 kHz  
Watchdog and sleep timers  
User-configurable low-voltage detection (LVD)  
Advanced peripherals (PSoC® Blocks)  
Six rail-to-rail analog PSoC blocks provide:  
• Up to 14-bit analog-to-digital converters (ADCs)  
• Up to 9-bit digital-to-analog converters (DACs)  
• Programmable gain amplifiers (PGAs)  
• Programmable filters and comparators  
Logic Block Diagram  
Analog  
Drivers  
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0  
Port 7  
Four digital PSoC blocks provide:  
• 8- to 32-bit timers, counters, and pulse width modulators  
(PWMs)  
• Cyclical redundancy check (CRC) and pseudo random  
sequence (PRS) modules  
Global Digital Interconnect  
Global Analog Interconnect  
• Full-duplex universal asynchronous receiver transmitter  
(UART)  
• Multiple serial peripheral interface (SPI) masters or slaves  
• Connectable to all general-purpose I/O (GPIO) pins  
Complex peripherals by combining blocks  
PSoC CORE  
SRAM  
1K  
SROM Flash16 KB  
Sleep and  
Watchdog  
CPU Core (M8C)  
Interrupt  
Controller  
Clock Sources  
(Includes IMO and ILO)  
Capacitive sensing application (CSA) capability  
Full speed USB (12 Mbps)  
Four unidirectional endpoints  
One bidirectional control endpoint  
USB 2.0 compliant  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref.  
Dedicated 256 byte buffer  
No external crystal required  
Digital  
Block  
Array  
Analog  
Block  
Array  
Flexible on-chip memory  
16 KB flash program storage 50,000 erase and write cycles  
1 KB static random access memory (SRAM) data storage  
ISSP  
Partial flash updates  
Flexible protection modes  
Electrically erasable programmable read-only memory  
(EEPROM) emulation in flash  
Analog  
Input  
Muxing  
Internal  
Voltage USB  
Ref.  
Digital  
2
Decimator  
POR and LVD  
System Resets  
I2 C  
Clocks MACs Type 2  
SYSTEM RESOURCES  
Programmable pin configurations  
25-mA sink, 10-mA source on all GPIOs  
Pull-up, pull-down, high Z, strong, or open-drain drive modes  
on all GPIOs  
Errata: For information on silicon errata, see “Errata” on page 64. Details include trigger conditions, devices affected, and proposed workaround.  
Cypress Semiconductor Corporation  
Document Number: 38-12018 Rev. AM  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 4, 2017  
 

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