PSoC® Mixed-Signal Array
Final Data Sheet
CY8C24123A,
CY8C24223A, and CY8C24423A
Features
■
Powerful Harvard Architecture Processor
■
■
Precision, Programmable Clocking
■
■
New CY8C24x23A PSoC Device
❐
❐
❐
❐
❐
M8C Processor Speeds to 24 MHz
8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
2.4 to 5.25V Operating Voltage
Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
❐
❐
Internal ±2.5% 24/48 MHz Oscillator
High-Accuracy 24 MHz with Optional 32 kHz
Crystal and PLL
❐
❐
Derived from the CY8C24x23 Device
Low Power and Low Voltage (2.4V)
Additional System Resources
❐
❐
Optional External Oscillator, up to 24 MHz
Internal Oscillator for Watchdog and Sleep
2
❐
I C™ Slave, Master, and Multi-Master to
400 kHz
Flexible On-Chip Memory
❐
❐
❐
❐
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
❐
Industrial Temperature Range: -40°C to +85°C
❐
4K Flash Program Storage 50,000 Erase/Write
Cycles
■
Advanced Peripherals (PSoC Blocks)
❐
❐
❐
❐
❐
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
❐
6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
■
Complete Development Tools
❐
Free Development Software
(PSoC Designer™)
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
4 Digital PSoC Blocks Provide:
❐
Full-Featured, In-Circuit Emulator and
Programmer
❐
■
Programmable Pin Configurations
❐
❐
25 mA Sink on all GPIO
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
Complex Peripherals by Combining Blocks
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❐
❐
Full Speed Emulation
Complex Breakpoint Structure
128K Trace Memory
Pull Up, Pull Down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
Up to 10 Analog Inputs on GPIO
Two 30 mA Analog Outputs on GPIO
Configurable Interrupt on all GPIO
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❐
❐
❐
PSoC® Functional Overview
Analog
Drivers
Port 2 Port 1 Port 0
PSoC CORE
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
System Bus
Global Digital Interconnect
SRAM
Global Analog Interconnect
Flash 4K
SROM
256 Bytes
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C24x23A family can have up to three IO
ports that connect to the global digital and analog interconnects,
providing access to 4 digital blocks and 6 analog blocks.
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref
Digital
Block
Array
Analog
Block
Array
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
Internal
Voltage
Ref.
Switch
Mode
Pump
Digital
Clocks Accum.
Multiply
POR and LVD
System Resets
I2C
Decimator
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
SYSTEM RESOURCES
October 17, 2006
© Cypress Semiconductor Corp. 2004-2006 — Document No. 38-12028 Rev. *F
1
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