Datasheet > CY8C24123A_09

CY8C24123A_09

更新时间： 2022-12-28 02:46:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
55页	1570K
描述
PSoC Programmable System-on-Chip

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CY8C24123A_09 数据手册

CY8C24123A

CY8C24223A, CY8C24423A

PSoC^®Programmable System-on-Chip™

■ New CY8C24x23A PSoC Device

❐ Derived From the CY8C24x23 Device

❐ Low Power and Low Voltage (2.4V)

Features

■ Powerful Harvard Architecture Processor

❐ M8C Processor Speeds to 24 MHz

❐ 8x8 Multiply, 32-Bit Accumulate

❐ Low Power at High Speed

❐ 2.4 to 5.25V Operating Voltage

❐ Operating Voltages Down to 1.0V Using On-Chip Switch

Mode Pump (SMP)

■ Additional System Resources

❐ I²C™ Slave, Master, and MultiMaster to 400 kHz

❐ Watchdog and Sleep Timers

❐ User-Configurable Low Voltage Detection

❐ Integrated Supervisory Circuit

❐ On-Chip Precision Voltage Reference

❐ Industrial Temperature Range: -40°C to +85°C

■ Advanced Peripherals (PSoC^®Blocks)

❐ Six Rail-to-Rail Analog PSoC Blocks Provide:

• Up to 14-Bit ADCs

■ Complete Development Tools

❐ Free Development Software (PSoC Designer™)

❐ Full-Featured, In-Circuit Emulator, and Programmer

❐ Full Speed Emulation

❐ Complex Breakpoint Structure

❐ 128K Trace Memory

• Up to 9-Bit DACs

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

❐ Four Digital PSoC Blocks Provide:

• 8 to 32-Bit Timers, Counters, and PWMs

• CRC and PRS Modules

Logic Block Diagram

Analog

Port 2 Port 1 Port 0

Drivers

• Full-Duplex UART

PSoC CORE

• Multiple SPI Masters or Slaves

• Connectable to All GPIO Pins

❐ Complex Peripherals by Combining Blocks

System Bus

■ Precision, Programmable Clocking

Global Digital Interconnect

Global Analog Interconnect

❐ Internal ±2.5% 24/48 MHz Oscillator

SRAM

256 Bytes

SROM

Flash 4K

❐ High accuracy 24 MHz with optional 32 kHz Crystal and PLL

❐ Optional External Oscillator, up to 24 MHz

❐ Internal Oscillator for Watchdog and Sleep

Sleep and

Watchdog

CPU Core (M8C)

Interrupt

Controller

■ Flexible On-Chip Memory

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

❐ 4K Flash Program Storage 50,000 Erase/Write Cycles

❐ 256 Bytes SRAM Data Storage

❐ In-System Serial Programming (ISSP)

❐ Partial Flash Updates

❐ Flexible Protection Modes

❐ EEPROM Emulation in Flash

DIGITAL SYSTEM

ANALOG SYSTEM

Analog

Ref

Digital

Block

Array

Analog

Block

Array

Analog

Input

Muxing

■ Programmable Pin Configurations

❐ 25 mA Sink on all GPIO

❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive

Modes on All GPIO

❐ Up to Ten Analog Inputs on GPIO

❐ Two 30 mA Analog Outputs on GPIO

❐ Configurable Interrupt on All GPIO

Internal

Voltage

Ref.

Switch

Mode

Pump

Digital

Clocks Accum.

Multiply

POR and LVD

System Resets

I²C

Decimator

SYSTEM RESOURCES

Cypress Semiconductor Corporation

Document Number: 38-12028 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 14, 2009

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