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CY8C24123-24SI

更新时间： 2024-11-20 04:53:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
41页 618K
描述
PSoC Mixed Signal Array

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CY8C24123-24SI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：0.150 INCH, MS-012, SOIC-8
针数：8Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.21
地址总线宽度：位大小：8
边界扫描：NOCPU系列：M8C
最大时钟频率：24.24 MHz外部数据总线宽度：
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：4.889 mm湿度敏感等级：1
I/O 线路数量：6端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：220
电源：3.3/5 V认证状态：Not Qualified
RAM（字节）：256RAM（字数）：256
ROM（单词）：4096ROM可编程性：FLASH
座面最大高度：1.727 mm速度：24 MHz
子类别：Microcontrollers最大压摆率：8 mA
最大供电电压：5.25 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.8985 mm
Base Number Matches：1

CY8C24123-24SI 数据手册

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PSoC™ Mixed Signal Array  
Final Data Sheet  
CY8C24123, CY8C24223, and CY8C24423  
Features  
■
Powerful Harvard Architecture Processor  
■
■
Precision, Programmable Clocking  
■
Additional System Resources  
❐
I2CSlave, Master, and Multi-Master to  
❐
❐
❐
❐
❐
M8C Processor Speeds to 24 MHz  
8x8 Multiply, 32-Bit Accumulate  
Low Power at High Speed  
3.0 to 5.25 V Operating Voltage  
Operating Voltages Down to 1.0V Using On-  
Chip Switch Mode Pump (SMP)  
❐
❐
Internal ±2.5% 24/48 MHz Oscillator  
High-Accuracy 24 MHz with Optional 32 kHz  
Crystal and PLL  
400 kHz  
❐
❐
❐
❐
Watchdog and Sleep Timers  
User-Configurable Low Voltage Detection  
Integrated Supervisory Circuit  
❐
❐
Optional External Oscillator, up to 24 MHz  
Internal Oscillator for Watchdog and Sleep  
On-Chip Precision Voltage Reference  
Flexible On-Chip Memory  
❐
Industrial Temperature Range: -40°C to +85°C  
❐
4K Bytes Flash Program Storage 50,000  
Erase/Write Cycles  
■
Complete Development Tools  
■
Advanced Peripherals (PSoC Blocks)  
❐
Free Development Software  
(PSoC™ Designer)  
❐
❐
❐
❐
❐
256 Bytes SRAM Data Storage  
In-System Serial Programming (ISSP)  
Partial Flash Updates  
Flexible Protection Modes  
EEPROM Emulation in Flash  
❐
6 Rail-to-Rail Analog PSoC Blocks Provide:  
- Up to 14-Bit ADCs  
- Up to 8-Bit DACs  
❐
Full-Featured, In-Circuit Emulator and  
Programmer  
❐
❐
❐
Full Speed Emulation  
Complex Breakpoint Structure  
128K Bytes Trace Memory  
- Programmable Gain Amplifiers  
- Programmable Filters and Comparators  
4 Digital PSoC Blocks Provide:  
❐
■
Programmable Pin Configurations  
❐
❐
25 mA Sink on all GPIO  
- 8- to 32-Bit Timers, Counters, and PWMs  
- CRC and PRS Modules  
- Full-Duplex UART  
- Multiple SPIMasters or Slaves  
- Connectable to all GPIO Pins  
Pull up, Pull down, High Z, Strong, or Open  
Drain Drive Modes on all GPIO  
Up to 10 Analog Inputs on GPIO  
Two 30 mA Analog Outputs on GPIO  
Configurable Interrupt on all GPIO  
❐
❐
❐
❐
Complex Peripherals by Combining Blocks  
Analog  
Drivers  
PSoC™ Functional Overview  
Port 2 Port 1 Port 0  
PSoC CORE  
The PSoC™ family consists of many Mixed Signal Array with  
On-Chip Controller devices. These devices are designed to  
replace multiple traditional MCU-based system components  
with one, low cost single-chip programmable device. PSoC  
devices include configurable blocks of analog and digital logic,  
as well as programmable interconnects. This architecture  
allows the user to create customized peripheral configurations  
that match the requirements of each individual application.  
Additionally, a fast CPU, Flash program memory, SRAM data  
memory, and configurable IO are included in a range of conve-  
nient pinouts and packages.  
System Bus  
Global Digital Interconnect  
SRAM  
Global Analog Interconnect  
Flash 4K  
SROM  
256 Bytes  
Sleep and  
Watchdog  
CPU Core (M8C)  
Interrupt  
Controller  
Multiple Clock Sources  
(Includes IMO, ILO, PLL, and ECO)  
The PSoC architecture, as illustrated on the left, is comprised of  
four main areas: PSoC Core, Digital System, Analog System,  
and System Resources. Configurable global busing allows all  
the device resources to be combined into a complete custom  
system. The PSoC CY8C24x23 family can have up to three IO  
ports that connect to the global digital and analog interconnects,  
providing access to 4 digital blocks and 6 analog blocks.  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref  
Analog  
Block  
Array  
Digital  
Block Array  
(1 Rows,  
4 Blocks)  
(2 Columns,  
6 Blocks)  
Analog  
Input  
Muxing  
The PSoC Core  
The PSoC Core is a powerful engine that supports a rich fea-  
ture set. The core includes a CPU, memory, clocks, and config-  
urable GPIO (General Purpose IO).  
POR and LVD Internal  
Voltage  
Switch  
Mode  
Pump  
Digital  
Clocks Accum.  
Multiply  
I2C  
Decimator  
System Resets  
Ref.  
The M8C CPU core is a powerful processor with speeds up to  
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-  
SYSTEM RESOURCES  
June 2004  
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12011 Rev. *F  
1
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中文翻译

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CY8C24123-24SI 替代型号

型号 品牌 替代类型 描述 数据表
CY8C22113-24SI CYPRESS

完全替代

 PSoC Mixed Signal Array
CY8C22113-24SXI CYPRESS

功能相似

 Multifunction Peripheral, CMOS, PDSO8, 0.150 INCH, MS-012, SOIC-8
CY8C24123A-24SXI CYPRESS

功能相似

 PSoC Mixed-Signal Array

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