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CY8C24094-24LTXIT PDF预览

CY8C24094-24LTXIT

更新时间: 2024-11-24 06:51:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
50页 1561K
描述
PSoC® Programmable System-on-Chip

CY8C24094-24LTXIT 数据手册

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CY8C24094, CY8C24794  
CY8C24894, CY8C24994  
PSoC® Programmable System-on-Chip  
Full Speed USB (12 Mbps)  
Four Uni-Directional Endpoints  
One Bi-Directional Control Endpoint  
USB 2.0 Compliant  
1. Features  
XRES Pin to Support In-System Serial Programming (ISSP)  
and External Reset Control in CY8C24894  
Dedicated 256 Byte Buffer  
No External Crystal Required  
Powerful Harvard Architecture Processor  
M8C Processor Speeds to 24 MHz  
Two 8x8 Multiply, 32-Bit Accumulate  
Low Power at High Speed  
3V to 5.25V Operating Voltage  
Industrial Temperature Range: -40°C to +85°C  
USB Temperature Range: -10°C to +85°C  
Flexible On-Chip Memory  
16K Flash Program Storage 50,000 Erase and Write Cycles  
1K SRAM Data Storage  
In-System Serial Programming (ISSP)  
Partial Flash Updates  
Advanced Peripherals (PSoC® Blocks)  
6 Rail-to-Rail Analog PSoC Blocks Provide:  
• Up to 14-Bit ADCs  
Flexible Protection Modes  
EEPROM Emulation in Flash  
Programmable Pin Configurations  
• Up to 9-Bit DACs  
25 mA Sink, 10 mA Source on all GPIO  
• Programmable Gain Amplifiers  
• Programmable Filters and Comparators  
Four Digital PSoC Blocks Provide:  
• 8 to 32-Bit Timers, Counters, and PWMs  
• CRC and PRS Modules  
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive  
Modes on all GPI/O  
Up to 48 Analog Inputs on GPI/O  
Two 33 mA Analog Outputs on GPI/O  
Configurable Interrupt on all GPI/O  
Precision, Programmable Clocking  
• Full-Duplex UART  
Internal ±4% 24 and 48 MHz Oscillator  
Internal Oscillator for Watchdog and Sleep  
0.25% Accuracy for USB with no External Components  
• Multiple SPIMasters or Slaves  
• Connectable to all GPI/O Pins  
Complex Peripherals by Combining Blocks  
Capacitive Sensing Application Capability  
Additional System Resources  
I2C Slave, Master, and Multi-Master to 400 kHz  
Watchdog and Sleep Timers  
User Configurable Low Voltage Detection  
A n a lo g  
P o r t  
5
P o r t  
4
P o r t  
3
P o r t  
2
P o r t  
1
P o r t 0  
P o r t  
7
D
r iv e r s  
Logic Block Diagram  
G lo b a l D ig ita l In t e r c o n n e c t  
G lo b a l A n a lo g In te r c o n n e c t  
P S o C C O R E  
S R A M  
1 K  
S R O M  
F la s h 1 6 K  
S le e p a n d  
a tc h d o g  
C P U C o r e ( M 8 C )  
W
In t e r r u p t  
C o n tr o lle r  
C lo c k S o u r c e s  
( I n c lu d e s IM O a n d I L O )  
D IG IT A L S Y S T E M  
A N A L O G S Y S T E M  
A n a lo g  
R e f.  
D i g it a l  
B lo c k  
A r r a y  
A n a l o g  
B lo c k  
A r r a y  
In te r n a l  
V o lta g e  
R e f.  
A n a lo g  
In p u t  
D ig ita l  
C lo c k s  
2
D e c im a to r  
T y p e  
P O R a n d L V D  
S y s te m R e s e t s  
I 2 C  
U S B  
M
A C s  
2
M
u x in g  
S Y S T E M R E S O U R C E S  
Cypress Semiconductor Corporation  
Document Number: 38-12018 Rev. *U  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 30, 2010  
[+] Feedback  

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