Datasheet > CY7C1512KV18-250BZCT

CY7C1512KV18-250BZCT

更新时间： 2024-11-29 19:45:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
35页	638K
描述
Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165

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CY7C1512KV18-250BZCT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	包装说明：	LBGA, BGA165,11X15,40
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.24
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE; IT ALSO OPERATES AT 1.5V
最大时钟频率 (fCLK)：	250 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	15 mm	内存密度：	75497472 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	235	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.65 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	20
宽度：	13 mm	Base Number Matches：	1

CY7C1512KV18-250BZCT 数据手册

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CY7C1525KV18

CY7C1512KV18

CY7C1514KV18

72-Mbit QDR^®II SRAM Two-Word

Burst Architecture

72-Mbit QDR^®II SRAM Two-Word Burst Architecture

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

CY7C1525KV18 – 8M × 9

CY7C1512KV18 – 4M × 18

CY7C1514KV18 – 2M × 36

■ 350 MHz clock for high bandwidth

■ Two-word burst on all accesses

Functional Description

■ Double data rate (DDR) interfaces on both read and write ports

(data transferred at 700 MHz) at 350 MHz

The CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18

are 1.8 V synchronous pipelined SRAMs, equipped with QDR II

architecture. QDR II architecture consists of two separate ports:

the read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR II architecture has separate data inputs and

data outputs to completely eliminate the need to “turnaround” the

data bus that exists with common I/O devices. Access to each

port is through a common address bus. Addresses for read and

write addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the QDR II read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with 9-bit words

(CY7C1525KV18), 18-bit words (CY7C1512KV18), or 36-bit

words (CY7C1514KV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus turnarounds.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR^®II operates with 1.5 cycle read latency when DOFF is

asserted HIGH

■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

■ Available in × 9, × 18, and × 36 configurations

■ Full data coherency, providing most current data

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Core V_DD= 1.8 V (±0.1 V); I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-ball fine pitch ball grid array (FBGA) package

(13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

For a complete list of related documentation, click here.

■ JTAG 1149.1 compatible test access port

■ Phase Locked Loop (PLL) for Accurate Data Placement

Selection Guide

Description

Maximum operating frequency

Maximum operating current

350 MHz

350

333 MHz

333

300 MHz

300

250 MHz Unit

250

640

650

790

MHz

× 9 Not Offered

790

730

× 18

840

810

750

× 36 Not Offered

990

910

Cypress Semiconductor Corporation

Document Number: 001-00436 Rev. *V

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 19, 2018

12 3 4 5 6 7...35

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CY7C1512KV18-250BZCT 替代型号

型号	品牌	替代类型	描述	数据表
CY7C1512KV18-250BZXC	CYPRESS	完全替代	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18-250BZC	CYPRESS	完全替代	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512AV18-250BZXC	CYPRESS	完全替代	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur

与CY7C1512KV18-250BZCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1512KV18-250BZI	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18-250BZI	INFINEON	获取价格	Synchronous SRAM
CY7C1512KV18-250BZIT	CYPRESS	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1512KV18-250BZIT	INFINEON	获取价格	Synchronous SRAM
CY7C1512KV18-250BZXC	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18-250BZXC	INFINEON	获取价格	Synchronous SRAM
CY7C1512KV18-250BZXI	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18-250BZXI	INFINEON	获取价格	Synchronous SRAM
CY7C1512KV18-250BZXIT	CYPRESS	获取价格	暂无描述
CY7C1512KV18-250BZXIT	INFINEON	获取价格	Synchronous SRAM

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