Datasheet > CY7C1512KV18-300BZC

CY7C1512KV18-300BZC

更新时间： 2024-11-29 06:51:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	815K
描述
72-Mbit QDR-II SRAM 2-Word Burst Architecture

阅读下载

中文翻译

获取价格

技术参数
数据手册
替代型号

如果您发现信息不准确，欢迎纠错

CY7C1512KV18-300BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LBGA, BGA165,11X15,40	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	Factory Lead Time：	1 week
风险等级：	1.64	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE; IT ALSO OPERATES AT 1.5V	最大时钟频率 (fCLK)：	300 MHz
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	75497472 bit	内存集成电路类型：	QDR SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	4194304 words	字数代码：	4000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	4MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	235
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.75 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	13 mm
Base Number Matches：	1

CY7C1512KV18-300BZC 数据手册

浏览型号CY7C1512KV18-300BZC的Datasheet PDF文件第2页

浏览型号CY7C1512KV18-300BZC的Datasheet PDF文件第3页

浏览型号CY7C1512KV18-300BZC的Datasheet PDF文件第4页

浏览型号CY7C1512KV18-300BZC的Datasheet PDF文件第5页

浏览型号CY7C1512KV18-300BZC的Datasheet PDF文件第6页

浏览型号CY7C1512KV18-300BZC的Datasheet PDF文件第7页

CY7C1510KV18, CY7C1525KV18

CY7C1512KV18, CY7C1514KV18

72-Mbit QDR™-II SRAM 2-Word

Burst Architecture

Features

Configurations

■ Separate Independent Read and Write Data Ports

❐ Supports concurrent transactions

CY7C1510KV18 – 8M x 8

CY7C1525KV18 – 8M x 9

CY7C1512KV18 – 4M x 18

CY7C1514KV18 – 2M x 36

■ 333 MHz Clock for High Bandwidth

■ 2-word Burst on all Accesses

■ Double Data Rate (DDR) Interfaces on both Read and Write

Ports (data transferred at 666 MHz) at 333 MHz

Functional Description

The CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and

CY7C1514KV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II architecture. QDR-II architecture consists

of two separate ports: the read port and the write port to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR-II architecture has

separate data inputs and data outputs to completely eliminate

the need to “turnaround” the data bus that exists with common

I/O devices. Access to each port is through a common address

bus. Addresses for read and write addresses are latched on

alternate rising edges of the input (K) clock. Accesses to the

QDR-II read and write ports are completely independent of one

another. To maximize data throughput, both read and write ports

are equipped with DDR interfaces. Each address location is

associated with two 8-bit words (CY7C1510KV18), 9-bit words

(CY7C1525KV18), 18-bit words (CY7C1512KV18), or 36-bit

words (CY7C1514KV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus turnarounds.

■ Two Input Clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Single Multiplexed Address Input bus latches Address Inputs

for both Read and Write Ports

■ Separate Port Selects for Depth Expansion

■ Synchronous internally Self-timed Writes

■ QDR™-II operates with 1.5 Cycle Read Latency when DOFF

is asserted HIGH

■ Operates similar to QDR-I Device with 1 Cycle Read Latency

when DOFF is asserted LOW

■ Available in x8, x9, x18, and x36 Configurations

■ Full Data Coherency, providing Most Current Data

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Core V_DD= 1.8V (±0.1V); IO V_DDQ= 1.4V to V_DD

❐ Supports both 1.5V and 1.8V IO supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ Variable Drive HSTL Output Buffers

■ JTAG 1149.1 Compatible Test Access Port

■ Phase Locked Loop (PLL) for Accurate Data Placement

Table 1. Selection Guide

Description

333 MHz

333

300 MHz

300

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

790

730

640

540

480

790

730

640

540

480

x18

x36

810

750

650

550

490

990

910

790

660

580

Cypress Semiconductor Corporation

Document Number: 001-00436 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 30, 2009

[+] Feedback

12 3 4 5 6 7...30

中文翻译

下载PDF

CY7C1512KV18-300BZC 替代型号

型号	品牌	替代类型	描述	数据表
CY7C1512KV18-300BZXC	CYPRESS	完全替代	72-Mbit QDR-II SRAM 2-Word Burst Architecture
IS61QDB24M18A-300M3L	ISSI	功能相似	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165

与CY7C1512KV18-300BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1512KV18-300BZI	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18-300BZXC	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18-300BZXC	INFINEON	获取价格	Synchronous SRAM
CY7C1512KV18-300BZXI	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18-300BZXI	INFINEON	获取价格	Synchronous SRAM
CY7C1512KV18-333BZC	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18-333BZI	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18-333BZXC	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18-333BZXC	INFINEON	获取价格	Synchronous SRAM
CY7C1512KV18-333BZXI	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture

与CY7C1512KV18-300BZC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

49
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

39
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

67
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

63

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1512KV18-300BZC

CY7C1512KV18-300BZC 技术参数

CY7C1512KV18-300BZC 数据手册

CY7C1512KV18-300BZC 替代型号

与CY7C1512KV18-300BZC相关器件

与CY7C1512KV18-300BZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1512KV18-300BZC

CY7C1512KV18-300BZC 技术参数

CY7C1512KV18-300BZC 数据手册

CY7C1512KV18-300BZC 替代型号

与CY7C1512KV18-300BZC相关器件

与CY7C1512KV18-300BZC相关文章

您还可以找

您在本页遇到什么问题？