Datasheet > CY7C1512V18

CY7C1512V18

更新时间： 2024-02-26 10:02:04

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
24页	359K
描述
72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture

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中文翻译

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数据手册

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CY7C1512V18 数据手册

CY7C1510V18

CY7C1525V18

CY7C1512V18

CY7C1514V18

PRELIMINARY

72-Mbit QDR-II™ SRAM 2-Word Burst Architecture

Features

Functional Description

• Separate Independent Read and Write Data Ports

The CY7C1510V18, CY7C1525V18, CY7C1512V18, and

CY7C1514V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II architecture. QDR-II architecture

consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read

operations and the Write Port has dedicated Data Inputs to

support Write operations. QDR-II architecture has separate

data inputs and data outputs to completely eliminate the need

to “turn-around” the data bus required with common I/O

devices. Access to each port is accomplished through a

common address bus. The Read address is latched on the

rising edge of the K clock and the Write address is latched on

— Supports concurrent transactions

• 200-MHz clock for high bandwidth

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and

Write ports (data transferred at 400 MHz) @ 200 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatching

the rising edge of the clock. Accesses to the QDR-II Read

• Echo clocks (CQ and CQ) simplify data capture in high

speed systems

and Write ports are completely independent of one another. In

order to maximize data throughput, both Read and Write ports

are equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with two 8-bit words

(CY7C1510V18) or 9-bit words (CY7C1525V18) or 18-bit

words (CY7C1512V18) or 36-bit words (CY7C1514V18) that

burst sequentially into or out of the device. Since data can be

transferred into and out of the device on every rising edge of

both input clocks (K and K and C and C), memory bandwidth

is maximized while simplifying system design by eliminating

bus “turn-arounds.”

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x9, x18, and x36 configurations

• Full data coherency, providing most current data

• Core V_DD= 1.8V(±0.1V);I/O V_DDQ= 1.4V to V_DD

• 15 × 17 × 1.4 mm 1.0-mm pitch FBGA package, 165-ball

(11 × 15 matrix)

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

• Variable drive HSTL output buffers

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1510V18 – 8M x 8

CY7C1525V18 – 8M x 9

CY7C1512V18 – 4M x 18

CY7C1514V18 – 2M x 36

Cypress Semiconductor Corporation

Document #: 38-05489 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 21, 2004

12 3 4 5 6 7...24

中文翻译

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与CY7C1512V18相关器件

型号	品牌	获取价格	描述	数据表
CY7C1512V18-167BZC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1512V18-167BZI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1512V18-167BZXC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1512V18-167BZXI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1512V18-167BZXIT	CYPRESS	获取价格	Standard SRAM, 4MX18, 0.5ns, CMOS, PBGA165
CY7C1512V18-200BZC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1512V18-200BZI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1512V18-200BZXC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1512V18-200BZXI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1512V18-250BZC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur

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