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CY7C1512KV18-350BZC PDF预览

CY7C1512KV18-350BZC

更新时间: 2024-01-29 02:44:01
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
33页 897K
描述
72-Mbit QDR II SRAM 2-Word Burst Architecture Two-word burst on all accesses

CY7C1512KV18-350BZC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
针数:165Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:5.78
Is Samacsys:N最长访问时间:0.45 ns
其他特性:PIPELINED ARCHITECTURE; IT ALSO OPERATES AT 1.5V最大时钟频率 (fCLK):350 MHz
I/O 类型:SEPARATEJESD-30 代码:R-PBGA-B165
JESD-609代码:e0长度:15 mm
内存密度:75497472 bit内存集成电路类型:QDR SRAM
内存宽度:18功能数量:1
端子数量:165字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA165,11X15,40封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:1.5/1.8,1.8 V
认证状态:Not Qualified座面最大高度:1.4 mm
最小待机电流:1.7 V子类别:SRAMs
最大压摆率:0.84 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:13 mmBase Number Matches:1

CY7C1512KV18-350BZC 数据手册

 浏览型号CY7C1512KV18-350BZC的Datasheet PDF文件第2页浏览型号CY7C1512KV18-350BZC的Datasheet PDF文件第3页浏览型号CY7C1512KV18-350BZC的Datasheet PDF文件第4页浏览型号CY7C1512KV18-350BZC的Datasheet PDF文件第5页浏览型号CY7C1512KV18-350BZC的Datasheet PDF文件第6页浏览型号CY7C1512KV18-350BZC的Datasheet PDF文件第7页 
CY7C1510KV18, CY7C1525KV18  
CY7C1512KV18, CY7C1514KV18  
72-Mbit QDR® II SRAM 2-Word  
Burst Architecture  
Features  
Configurations  
Separate independent read and write data ports  
Supports concurrent transactions  
CY7C1510KV18 – 8M x 8  
CY7C1525KV18 – 8M x 9  
CY7C1512KV18 – 4M x 18  
CY7C1514KV18 – 2M x 36  
350 MHz clock for high bandwidth  
Two-word burst on all accesses  
Double data rate (DDR) interfaces on both read and write ports  
(data transferred at 700 MHz) at 350 MHz  
Functional Description  
The CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and  
CY7C1514KV18 are 1.8 V synchronous pipelined SRAMs,  
equipped with QDR II architecture. QDR II architecture consists  
of two separate ports: the read port and the write port to access  
the memory array. The read port has dedicated data outputs to  
support read operations and the write port has dedicated data  
inputs to support write operations. QDR II architecture has  
separate data inputs and data outputs to completely eliminate  
the need to “turnaround” the data bus that exists with common  
I/O devices. Access to each port is through a common address  
bus. Addresses for read and write addresses are latched on  
alternate rising edges of the input (K) clock. Accesses to the  
QDR II read and write ports are completely independent of one  
another. To maximize data throughput, both read and write ports  
are equipped with DDR interfaces. Each address location is  
associated with two 8-bit words (CY7C1510KV18), 9-bit words  
(CY7C1525KV18), 18-bit words (CY7C1512KV18), or 36-bit  
words (CY7C1514KV18) that burst sequentially into or out of the  
device. Because data can be transferred into and out of the  
device on every rising edge of both input clocks (K and K and C  
and C), memory bandwidth is maximized while simplifying  
system design by eliminating bus turnarounds.  
Two input clocks (K and K) for precise DDR timing  
SRAM uses rising edges only  
Two input clocks for output data (C and C) to minimize clock  
skew and flight time mismatches  
Echo clocks (CQ and CQ) simplify data capture in high speed  
systems  
Single multiplexed address input bus latches address inputs  
for both read and write ports  
Separate port selects for depth expansion  
Synchronous internally self-timed writes  
QDR® II operates with 1.5 cycle read latency when DOFF is  
asserted HIGH  
OperatessimilartoQDRIdevicewith1cyclereadlatencywhen  
DOFF is asserted LOW  
Available in x8, x9, x18, and x36 configurations  
Full data coherency, providing most current data  
Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4V to VDD  
Supports both 1.5 V and 1.8 V I/O supply  
Depth expansion is accomplished with port selects, which  
enables each port to operate independently.  
Available in 165-ball fine pitch ball grid array (FBGA) package  
(13 x 15 x 1.4 mm)  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C (or K or K in a single clock  
domain) input clocks. Writes are conducted with on-chip  
synchronous self-timed write circuitry.  
Offered in both Pb-free and non Pb-free packages  
Variable drive HSTL output buffers  
JTAG 1149.1 compatible test access port  
Phase Locked Loop (PLL) for Accurate Data Placement  
Table 1. Selection Guide  
Description  
Maximum operating frequency  
Maximum operating current  
350 MHz  
350  
333 MHz  
333  
300 MHz  
300  
250 MHz  
250  
200 MHz  
200  
167 MHz  
167  
Unit  
MHz  
mA  
x8  
x9  
825  
790  
730  
640  
540  
480  
825  
790  
730  
640  
540  
480  
x18  
x36  
840  
810  
750  
650  
550  
490  
1030  
990  
910  
790  
660  
580  
Cypress Semiconductor Corporation  
Document Number: 001-00436 Rev. *M  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 10, 2011  
[+] Feedback  

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