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CY7C1485V25-200BZXC PDF预览

CY7C1485V25-200BZXC

更新时间： 2024-09-19 05:19:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
26页 1149K
描述
72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

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中文翻译

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CY7C1485V25-200BZXC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA, QFP100,.63X.87针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
最长访问时间：3 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：200 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e3
长度：17 mm内存密度：75497472 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：1.8/2.5,2.5 V
认证状态：Not Qualified座面最大高度：1.4 mm
最小待机电流：2.38 V子类别：SRAMs
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：15 mm
Base Number Matches：1

CY7C1485V25-200BZXC 数据手册

 浏览型号CY7C1485V25-200BZXC的Datasheet PDF文件第2页浏览型号CY7C1485V25-200BZXC的Datasheet PDF文件第3页浏览型号CY7C1485V25-200BZXC的Datasheet PDF文件第4页浏览型号CY7C1485V25-200BZXC的Datasheet PDF文件第5页浏览型号CY7C1485V25-200BZXC的Datasheet PDF文件第6页浏览型号CY7C1485V25-200BZXC的Datasheet PDF文件第7页 
CY7C1484V25  
CY7C1485V25  
72-Mbit (2M x 36/4M x 18) Pipelined  
DCD Sync SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
The CY7C1484V25/CY7C1485V25 SRAM integrates 2M x  
36/4M x 18 SRAM cells with advanced synchronous  
peripheral circuitry and a two-bit counter for internal burst  
operation. All synchronous inputs are gated by registers  
controlled by a positive-edge-triggered Clock Input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
address-pipelining Chip Enable (CE1), depth-expansion Chip  
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP,  
and ADV), Write Enables (BWX and BWE), and Global Write  
(GW). Asynchronous inputs include the Output Enable (OE)  
and the ZZ pin.  
• Available speed grades are 250, 200, and 167 MHz  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (double cycle deselect)  
• Depth expansion without wait state  
• 2.5V core power supply (VDD  
)
• 2.5V/1.8V IO supply (VDDQ  
)
• Fast clock-to-output times  
— 3.0 ns (for 250-MHz device)  
Addresses and chip enables are registered at the rising edge  
of clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
• Provide high performance 3-1-1-1 access rate  
• User selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self timed writes  
Address, data inputs, and write controls are registered on-chip  
to initiate a self timed write cycle. This part supports byte write  
operations (see “Pin Definitions” on page 5 and “Truth Table”  
on page 8 for further details). Write cycles can be one to four  
bytes wide, as controlled by the byte write control inputs. GW  
active LOW causes all bytes to be written. This device incor-  
porates an additional pipelined enable register, which delays  
turning off the output buffers an additional cycle when a  
deselect is executed. This feature allows depth expansion  
without penalizing system performance.  
• Asynchronous output enable  
• CY7C1484V25, CY7C1485V25 available in JEDEC-  
standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free  
165-ball FBGA package  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode option  
The CY7C1484V25/CY7C1485V25 operates from a +2.5V  
core power supply while all outputs operate with a +2.5V or a  
+1.8V supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
250 MHz  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
3.0  
450  
120  
Maximum Operating Current  
Maximum CMOS Standby Current  
450  
400  
mA  
mA  
120  
120  
Note  
1. For best practices recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 38-05286 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 24, 2007  
[+] Feedback  
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