Datasheet > 存储 > SRAM> CY7C1485V33-200BZC

CY7C1485V33-200BZC

更新时间： 2024-11-07 22:07:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	508K
描述
2M x 36/4M x 18 Pipelined DCD SRAM

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技术参数
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CY7C1485V33-200BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	15 X 17 MM, 1.40 MM HEIGHT, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	3 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	17 mm	内存密度：	75497472 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最小待机电流：	3.14 V	子类别：	SRAMs
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	15 mm

CY7C1485V33-200BZC 数据手册

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CY7C1484V33

CY7C1485V33

PRELIMINARY

2M x 36/4M x 18 Pipelined DCD SRAM

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE), burst control

inputs (ADSC, ADSP, and ADV), write enables (BW_a, BW_b,

BW_c, BW_d, and BWE), and Global Write (GW).

Features

• Fast clock speed: 250, 200, and 167 MHz

• Provide high-performance 3-1-1-1 access rate

• Fast access time: 2.6, 3.0, and 3.4 ns

• Optimal for depth expansion

• Single 3.3V –5% and +5% power supply V_DD

• Separate V_DDQfor 3.3V or 2.5V

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Chip enable for address pipeline

• Address, data, and control registers

• Internally self-timed Write Cycle

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data (DQx) and the data

parity (DPx) outputs, enabled by OE, are also asynchronous.

DQa,b,c,d and DPa,b,c,d apply to CY7C1484V33 and DQa,b

and DPa,b apply to CY7C1485V33. a, b, c, and d each are

eight bits wide in the case of DQ and one bit wide in the case

of DP.

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

Pin (ADV).

• Burst control pins (interleaved or linear burst

sequence)

• Automatic power-down for portable applications

• High-density, high-speed packages

Address, data inputs, and write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BW_a

• JTAG boundary scan for BGA packaging version

• Available in 119-ball bump BGA and 100-pin TQFP

packages (CY7C1484V33 and CY7C1485V33).

• 165-ball FBGA will be offered on an opportunity basis.

(Please contact Cypress sales or marketing)

controls DQa and DPa. BW_bcontrols DQ and DP . BW

controls DQc and DPd. BW_dcontrols DQ and DPd. BW_a, BW_b^c,

BW_c, BW_dcan be active only with BWE being LOW. GW being

LOW causes all bytes to be written. Write pass-through

capability allows written data available at the output for the

immediately next Read cycle. This device also incorporates

pipelined enable circuit for easy depth expansion without

penalizing system performance.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

single-layer polysilicon, triple-layer metal technology. Each

memory cell consists of six transistors.

The CY7C1484V33 and CY7C1485V33 SRAMs integrate

2,097,152 × 36/4,194,304 × 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

The CY7C1484V33/CY7C1485V33 are both double-cycle

deselect parts.All inputs and outputs of the CY7C1484V33,

CY7C1485V33 are JEDEC standard JESD8-5-compatible.

Selection Guide

CY7C1484V33-

250

CY7C1485V33-

250

CY7C1484V33-

200

CY7C1485V33-

200

CY7C1484V33-

167

CY7C1485V33-

167

Unit

Maximum Access Time

2.6

3.0

3.4

Maximum Operating Current

TBD

Maximum CMOS Standby Current

Shaded areas contain advance information.

Cypress Semiconductor Corporation

Document #: 38-05285 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 18, 2003

12 3 4 5 6 7...29

中文翻译

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与CY7C1485V33-200BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1485V33-200BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1485V33-200BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1485V33-200BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1485V33-250AC	CYPRESS	获取价格	2M x 36/4M x 18 Pipelined DCD SRAM
CY7C1485V33-250AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1485V33-250AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1485V33-250BGC	CYPRESS	获取价格	2M x 36/4M x 18 Pipelined DCD SRAM
CY7C1485V33-250BZC	CYPRESS	获取价格	2M x 36/4M x 18 Pipelined DCD SRAM
CY7C1485V33-250BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1485V33-250BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

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