Datasheet > CY7C1485V33

CY7C1485V33

更新时间： 2024-09-18 22:24:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	508K
描述
2M x 36/4M x 18 Pipelined DCD SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1485V33 数据手册

CY7C1484V33

CY7C1485V33

PRELIMINARY

2M x 36/4M x 18 Pipelined DCD SRAM

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE), burst control

inputs (ADSC, ADSP, and ADV), write enables (BW_a, BW_b,

BW_c, BW_d, and BWE), and Global Write (GW).

Features

• Fast clock speed: 250, 200, and 167 MHz

• Provide high-performance 3-1-1-1 access rate

• Fast access time: 2.6, 3.0, and 3.4 ns

• Optimal for depth expansion

• Single 3.3V –5% and +5% power supply V_DD

• Separate V_DDQfor 3.3V or 2.5V

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Chip enable for address pipeline

• Address, data, and control registers

• Internally self-timed Write Cycle

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data (DQx) and the data

parity (DPx) outputs, enabled by OE, are also asynchronous.

DQa,b,c,d and DPa,b,c,d apply to CY7C1484V33 and DQa,b

and DPa,b apply to CY7C1485V33. a, b, c, and d each are

eight bits wide in the case of DQ and one bit wide in the case

of DP.

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

Pin (ADV).

• Burst control pins (interleaved or linear burst

sequence)

• Automatic power-down for portable applications

• High-density, high-speed packages

Address, data inputs, and write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BW_a

• JTAG boundary scan for BGA packaging version

• Available in 119-ball bump BGA and 100-pin TQFP

packages (CY7C1484V33 and CY7C1485V33).

• 165-ball FBGA will be offered on an opportunity basis.

(Please contact Cypress sales or marketing)

controls DQa and DPa. BW_bcontrols DQ and DP . BW

controls DQc and DPd. BW_dcontrols DQ and DPd. BW_a, BW_b^c,

BW_c, BW_dcan be active only with BWE being LOW. GW being

LOW causes all bytes to be written. Write pass-through

capability allows written data available at the output for the

immediately next Read cycle. This device also incorporates

pipelined enable circuit for easy depth expansion without

penalizing system performance.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

single-layer polysilicon, triple-layer metal technology. Each

memory cell consists of six transistors.

The CY7C1484V33 and CY7C1485V33 SRAMs integrate

2,097,152 × 36/4,194,304 × 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

The CY7C1484V33/CY7C1485V33 are both double-cycle

deselect parts.All inputs and outputs of the CY7C1484V33,

CY7C1485V33 are JEDEC standard JESD8-5-compatible.

Selection Guide

CY7C1484V33-

250

CY7C1485V33-

250

CY7C1484V33-

200

CY7C1485V33-

200

CY7C1484V33-

167

CY7C1485V33-

167

Unit

Maximum Access Time

2.6

3.0

3.4

Maximum Operating Current

TBD

Maximum CMOS Standby Current

Shaded areas contain advance information.

Cypress Semiconductor Corporation

Document #: 38-05285 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 18, 2003

12 3 4 5 6 7...29

中文翻译

下载PDF

与CY7C1485V33相关器件

型号	品牌	获取价格	描述	数据表
CY7C1485V33-167AC	CYPRESS	获取价格	2M x 36/4M x 18 Pipelined DCD SRAM
CY7C1485V33-167AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1485V33-167AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1485V33-167BGC	CYPRESS	获取价格	2M x 36/4M x 18 Pipelined DCD SRAM
CY7C1485V33-167BZC	CYPRESS	获取价格	2M x 36/4M x 18 Pipelined DCD SRAM
CY7C1485V33-167BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1485V33-167BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1485V33-167BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
CY7C1485V33-200AC	CYPRESS	获取价格	2M x 36/4M x 18 Pipelined DCD SRAM
CY7C1485V33-200AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

与CY7C1485V33相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

26
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

24
SL74HC10N：高性能三输入与非门解析
2024-09-03

99
AIC1781A 电池充电控制器深度解析
2024-09-03

91

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1485V33

CY7C1485V33 数据手册

与CY7C1485V33相关器件

与CY7C1485V33相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1485V33

CY7C1485V33 数据手册

与CY7C1485V33相关器件

与CY7C1485V33相关文章

您还可以找

您在本页遇到什么问题？