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CY7C1363C-100BGXI PDF预览

CY7C1363C-100BGXI

更新时间： 2024-11-16 03:57:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
31页 562K
描述
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

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CY7C1363C-100BGXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：22 X 14 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
针数：119Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.73最长访问时间：8.5 ns
其他特性：FLOW THROUGH ARCHITECTURE最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e1长度：22 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：119
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：2.4 mm最大待机电流：0.04 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.18 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：14 mmBase Number Matches：1

CY7C1363C-100BGXI 数据手册

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CY7C1361C  
CY7C1363C  
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM  
Features  
Functional Description[1]  
• Supports 100, 133-MHz bus operations  
• Supports 100-MHz bus operations (Automotive)  
• 256K × 36/512K × 18 common I/O  
The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36/512K x 18  
Synchronous Flow-through SRAMs, respectively designed to  
interface with high-speed microprocessors with minimum glue  
logic. Maximum access delay from clock rise is 6.5 ns  
(133-MHz version). A 2-bit on-chip counter captures the first  
address in a burst and increments the address automatically  
for the rest of the burst access. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst  
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx,  
and BWE), and Global Write (GW). Asynchronous inputs  
include the Output Enable (OE) and the ZZ pin.  
• 3.3V –5% and +10% core power supply (VDD  
)
• 2.5V or 3.3V I/O power supply (VDDQ  
)
• Fast clock-to-output times  
— 6.5 ns (133-MHz version)  
• Provide high-performance 2-1-1-1 access rate  
• User-selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
The CY7C1361C/CY7C1363C allows either interleaved or  
linear burst sequences, selected by the MODE input pin. A  
HIGH selects an interleaved burst sequence, while a LOW  
selects a linear burst sequence. Burst accesses can be  
initiated with the Processor Address Strobe (ADSP) or the  
cache Controller Address Strobe (ADSC) inputs. Address  
advancement is controlled by the Address Advancement  
(ADV) input.  
• Asynchronous output enable  
• Available in lead-free 100-Pin TQFP package, lead-free  
and non lead-free 119-Ball BGA package and 165-Ball  
FBGA package  
• TQFP Available with 3-Chip Enable and 2-Chip Enable  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
•“ZZ” Sleep Mode option  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
The CY7C1361C/CY7C1363C operates from a +3.3V core  
power supply while all outputs may operate with either a +2.5  
or +3.3V supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
250  
180  
mA  
mA  
mA  
Maximum CMOS Standby Current  
Comm/Ind’l  
Automotive  
40  
40  
60  
Notes:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.  
3
Cypress Semiconductor Corporation  
Document #: 38-05541 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 14, 2006  
[+] Feedback  
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