5秒后页面跳转
捷配首页

Datasheet > CY7C1363C-117BZC
CY7C1363C-117BZC PDF预览

CY7C1363C-117BZC

更新时间： 2024-11-16 09:44:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
30页 476K
描述
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

阅读下载

中文翻译

获取价格

CY7C1363C-117BZC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete包装说明：FBGA-165
Reach Compliance Code：compliant风险等级：5.92
最长访问时间：7.5 ns最大时钟频率 (fCLK)：117 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：9437184 bit内存集成电路类型：CACHE DRAM MODULE
内存宽度：18功能数量：1
端子数量：165字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.4 mm
最大待机电流：0.03 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.22 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

CY7C1363C-117BZC 数据手册

 浏览型号CY7C1363C-117BZC的Datasheet PDF文件第2页浏览型号CY7C1363C-117BZC的Datasheet PDF文件第3页浏览型号CY7C1363C-117BZC的Datasheet PDF文件第4页浏览型号CY7C1363C-117BZC的Datasheet PDF文件第5页浏览型号CY7C1363C-117BZC的Datasheet PDF文件第6页浏览型号CY7C1363C-117BZC的Datasheet PDF文件第7页 
CY7C1361C  
CY7C1363C  
PRELIMINARY  
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM  
Features  
Functional Description[1]  
• Supports 133-MHz bus operations  
• 256K × 36/512K × 18 common I/O  
• 3.3V –5% and +10% core power supply (VDD  
The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x  
18 Synchronous Flowthrough SRAMs, respectively designed  
to interface with high-speed microprocessors with minimum  
glue logic. Maximum access delay from clock rise is 6.5 ns  
(133-MHz version). A 2-bit on-chip counter captures the first  
address in a burst and increments the address automatically  
for the rest of the burst access. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
)
• 2.5V or 3.3V I/O supply (VDDQ  
• Fast clock-to-output times  
— 6.5 ns (133-MHz version)  
— 7.5 ns (117-MHz version)  
— 8.5 ns (100-MHz version)  
)
addresses, all data inputs, address-pipelining Chip Enable  
[2]  
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE3  
CE1  
2
Control inputs (  
,
,
), Write Enables  
(
ADV  
BWx  
and  
,
• Provide high-performance 2-1-1-1 access rate  
ADSC ADSP  
), and Global Write (  
BWE  
). Asynchronous  
GW  
and  
inputs  
• User-selectable burst counter supporting Intel  
(
)
and the ZZ pin  
OE  
.
include the Output Enable  
Pentiuminterleaved or linear burst sequences  
The CY7C1361C/CY7C1363C allows either interleaved or  
linear burst sequences, selected by the MODE input pin. A  
HIGH selects an interleaved burst sequence, while a LOW  
selects a linear burst sequence. Burst accesses can be  
initiated with the Processor Address Strobe (ADSP) or the  
cache Controller Address Strobe (ADSC) inputs. Address  
advancement is controlled by the Address Advancement  
(ADV) input.  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
• Asynchronous output enable  
• AvailableinLead-Free100TQFP,119BGAand165fBGA  
packages Both 2 and 3 Chip Enable Options for TQFP  
• IEEE 1149.1 compatible JTAG Boundary Scan for BGA  
and fBGA packages  
•“ZZ” Sleep Mode option  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (  
) or  
ADSP  
Address Strobe Controller (  
) are active. Subsequent  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
ADV  
The CY7C1361C/CY7C1363C operates from a +3.3V core  
power supply while all outputs may operate with either a +2.5  
or +3.3V supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
133 MHz  
117 MHz  
7.5  
100 MHz  
8.5  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
6.5  
250  
30  
220  
30  
180  
30  
Notes:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE is for A version of TQFP ( 3 Chip Enable Option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.  
3
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05541 Rev. *A  
Revised October 5, 2004  
1234567...30

中文翻译

下载PDF

与CY7C1363C-117BZC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1363C-117BZI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133AJXC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133AJXCT CYPRESS

获取价格

 		Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026,
CY7C1363C-133AJXI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133AJXIT CYPRESS

获取价格

 		Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026,
CY7C1363C-133AXC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133AXCT CYPRESS

获取价格

 		Standard SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-02
CY7C1363C-133AXI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133AXIT CYPRESS

获取价格

 		Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026,
CY7C1363C-133BGC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

与CY7C1363C-117BZC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证