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CY7C1363C-133AJXCT PDF预览

CY7C1363C-133AJXCT

更新时间： 2024-11-16 20:45:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
34页 877K
描述
Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100

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CY7C1363C-133AJXCT 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.35
最长访问时间：6.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
JESD-30 代码：R-PQFP-G100长度：20 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端子数量：100字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX18封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

CY7C1363C-133AJXCT 数据手册

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CY7C1361C/CY7C1363C  
9-Mbit (256 K × 36/512 K × 18)  
Flow-Through SRAM  
9-Mbit (256  
K × 36/512 K × 18) Flow-through SRAM  
Features  
Functional Description  
■ Supports 100 MHz, 133 MHz bus operations  
■ Supports 100 MHz bus operations (Automotive)  
■ 256 K × 36/512 K × 18 common I/O  
The CY7C1361C/CY7C1363C is a 3.3 V, 256 K × 36/512 K × 18  
synchronous flow-through SRAMs, respectively designed to  
interface with high speed microprocessors with minimum glue  
logic. Maximum access delay from clock rise is 6.5 ns (133 MHz  
version). A 2-bit on-chip counter captures the first address in a  
burst and increments the address automatically for the rest of the  
burst access. All synchronous inputs are gated by registers  
controlled by a positive-edge-triggered clock input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
address-pipelining chip enable (CE1), depth-expansion chip  
enables (CE2 and CE3[1]), burst control inputs (ADSC, ADSP,  
and ADV), write enables (BWx, and BWE), and global write  
(GW). Asynchronous inputs include the output enable (OE) and  
the ZZ pin.  
■ 3.3 V – 5% and +10% core power supply (VDD  
)
■ 2.5 V or 3.3 V I/O power supply (VDDQ  
)
■ Fast clock-to-output times  
❐ 6.5 ns (133-MHz version)  
■ Provide high performance 2-1-1-1 access rate  
■ User-selectable burst counter supporting IntelPentium  
interleaved or linear burst sequences  
The CY7C1361C/CY7C1363C enables either interleaved or  
linear burst sequences, selected by the MODE input pin. A HIGH  
selects an interleaved burst sequence, while a LOW selects a  
linear burst sequence. Burst accesses can be initiated with the  
processor address strobe (ADSP) or the cache controller  
address strobe (ADSC) inputs. Address advancement is  
controlled by the address advancement (ADV) input.  
■ Separate processor and controller address strobes  
■ Synchronous self-timed write  
■ Asynchronous output enable  
■ Available in Pb-free 100-pin TQFP package and non Pb-free  
119-ball BGA package  
Addresses and chip enables are registered at rising edge of  
clock when either address strobe processor (ADSP) or address  
strobe controller (ADSC) are active. Subsequent burst  
addresses can be internally generated as controlled by the  
advance pin (ADV).  
■ TQFP available with 3-chip enable and 2-chip enable  
■ IEEE 1149.1 JTAG-compatible boundary scan  
■ “ZZ” sleep mode option  
The CY7C1361C/CY7C1363C operates from a +3.3 V core  
power supply while all outputs may operate with either a +2.5 or  
+3.3 V supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
Description  
Maximum access time  
133 MHz  
100 MHz Unit  
6.5  
250  
40  
–
8.5  
180  
40  
ns  
Maximum operating current  
mA  
mA  
mA  
Maximum CMOS standby current  
Commercial/Industrial  
Automotive  
60  
Note  
1. CE is for A version of 100-pin TQFP (3 Chip Enable Option). 119-ball BGA is offered only in 2 Chip Enable.  
3
Cypress Semiconductor Corporation  
Document Number: 38-05541 Rev. *N  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 3, 2013  
 
 
 
 
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CY7C1363C-133AJXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1363C-133AJXC CYPRESS

类似代替

 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

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CY7C1363C-133AJXI CYPRESS

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CY7C1363C-133AJXIT CYPRESS

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CY7C1363C-133BGXC CYPRESS

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 		9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133BGXI CYPRESS

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 		9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

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