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CY7C136-45JXC

更新时间： 2024-11-16 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
15页 455K
描述
Dual-Port SRAM, 2KX8, 45ns, CMOS, PQCC52, PLASTIC, LEAD FREE, LCC-52

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CY7C136-45JXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：LCC包装说明：HQCCN,
针数：52Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.74最长访问时间：45 ns
其他特性：AUTOMATIC POWER-DOWN; INTERRUPT FLAGJESD-30 代码：S-PQCC-N52
JESD-609代码：e3长度：19.1262 mm
内存密度：16384 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：8湿度敏感等级：3
功能数量：1端子数量：52
字数：2048 words字数代码：2000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：2KX8
封装主体材料：PLASTIC/EPOXY封装代码：HQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：19.1262 mm
Base Number Matches：1

CY7C136-45JXC 数据手册

 浏览型号CY7C136-45JXC的Datasheet PDF文件第2页浏览型号CY7C136-45JXC的Datasheet PDF文件第3页浏览型号CY7C136-45JXC的Datasheet PDF文件第4页浏览型号CY7C136-45JXC的Datasheet PDF文件第5页浏览型号CY7C136-45JXC的Datasheet PDF文件第6页浏览型号CY7C136-45JXC的Datasheet PDF文件第7页 
CY7C132, CY7C136  
CY7C136A, CY7C142, CY7C146  
2K x 8 Dual-Port Static RAM  
Features  
Functional Description  
■ True dual-ported memory cells that enable simultaneous reads  
of the same memory location  
The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146  
are high speed CMOS 2K x 8 dual-port static RAMs. Two ports  
are provided to permit independent access to any location in  
memory. The CY7C132, CY7C136, and CY7C136A can be used  
as either a standalone 8-bit dual-port static RAM or as a  
MASTER dual-port RAM, in conjunction with the  
CY7C142/CY7C146 SLAVE dual-port device. They are used in  
systems that require 16-bit or greater word widths. This is the  
solution to applications that require shared or buffered data, such  
as cache memory for DSP, bit-slice, or multiprocessor designs.  
■ 2K x 8 organization  
■ 0.65 micron CMOS for optimum speed and power  
■ High speed access: 15 ns  
■ Low operating power: ICC = 110 mA (maximum)  
■ Fully asynchronous operation  
■ Automatic power down  
Each port has independent control pins; chip enable (CE), write  
enable (R/W), and output enable (OE). BUSY flags are provided  
on each port. In addition, an interrupt flag (INT) is provided on  
each port of the 52-pin PLCC version. BUSY signals that the port  
is trying to access the same location currently being accessed  
by the other port. On the PLCC version, INT is an interrupt flag  
indicating that data is placed in an unique location (7FF for the  
left port and 7FE for the right port).  
■ MasterCY7C132/CY7C136/CY7C136A[1] easilyexpandsdata  
bus width to 16 or more bits using slave CY7C142/CY7C146  
■ BUSY output flag on CY7C132/CY7C136/CY7C136A;  
BUSY input on CY7C142/CY7C146  
■ INT flag for port to port communication (52-Pin PLCC/PQFP  
versions)  
An automatic power down feature is controlled independently on  
each port by the chip enable (CE) pins.  
■ CY7C136, CY7C136A, and CY7C146 available in 52-pin  
PLCC and 52-pin PQFP packages  
■ Pb-free packages available  
Logic Block Diagram  
R/W  
L
R/W  
R
CE  
L
CE  
R
OE  
L
OE  
R
I/O  
I/O  
I/O  
I/O  
7L  
7R  
I/O  
CONTROL  
I/O  
CONTROL  
0R  
0L  
[2]  
[2]  
BUSY  
BUSY  
R
L
A
A
A
10L  
10R  
0R  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A
0L  
ARBITRATION  
LOGIC  
(7C132/7C136 ONLY)  
AND  
INTERRUPTLOGIC  
CE  
L
CE  
R
(7C136/7C146ONLY)  
OE  
L
OE  
R
R/W  
R/W  
R
L
[3]  
[3]  
INT  
L
INT  
R
Notes  
1. CY7C136 and CY7C136A are functionally identical.  
2. CY7C132/CY7C136/CY7C136A (Master): BUSY is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input.  
3. Open drain outputs; pull up resistor required.  
Cypress Semiconductor Corporation  
Document #: 38-06031 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised March 24, 2009  
[+] Feedback  
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