Datasheet > CY7C1363D-133AXI

CY7C1363D-133AXI

更新时间： 2024-11-16 12:52:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
22页	755K
描述
9-Mbit (512 K x 18) Flow-Through SRAM

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CY7C1363D-133AXI 数据手册

CY7C1363D

9-Mbit (512 K × 18) Flow-Through SRAM

9-Mbit (512

K × 18) Flow-Through SRAM

Features

Functional Description

■ Supports 133 MHz bus operations

■ 512 K × 18 common I/O

The CY7C1363D is a 3.3 V, 512 K × 18 synchronous flow-through

SRAM, respectively designed to interface with high speed

microprocessors with minimum glue logic. Maximum access

delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

counter captures the first address in a burst and increments the

address automatically for the rest of the burst access. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered clock input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

chip enable (CE₁), depth-expansion chip enables (CE₂and

CE₃^[1]), burst control inputs (ADSC, ADSP, and ADV), write

enables (BW_x, and BWE), and global write (GW). Asynchronous

inputs include the output enable (OE) and the ZZ pin.

■ 3.3 V – 5% and +10% core power supply (V_DD

)

■ 2.5 V or 3.3 V I/O power supply (V_DDQ

)

■ Fast clock-to-output times

❐ 6.5 ns (133-MHz version)

■ Provide high performance 2-1-1-1 access rate

■ User-selectable burst counter supporting Intel^Pentium^

interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed write

The CY7C1363D enables either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses can be initiated with the processor

address strobe (ADSP) or the cache controller address strobe

(ADSC) inputs. Address advancement is controlled by the

address advancement (ADV) input.

■ Asynchronous output enable

■ Available in Pb-free 100-pin TQFP package

■ TQFP available with 3-chip enable

■ “ZZ” sleep mode option

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV).

The CY7C1363D operates from a +3.3 V core power supply

while all outputs may operate with either a +2.5 or +3.3 V supply.

All

inputs

and

outputs

are

JEDEC-standard

JESD8-5-compatible.

Selection Guide

Description

Maximum access time

133 MHz Unit

6.5

250

Maximum operating current

Maximum CMOS standby current

Industrial

Note

1. CE is for A version of 100-pin TQFP (3 Chip Enable Option).

Cypress Semiconductor Corporation

Document Number: 001-86215 Rev. **

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 20, 2013

12 3 4 5 6 7...22

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与CY7C1363D-133AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C136-45JC	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C136-45JCR	CYPRESS	获取价格	暂无描述
CY7C136-45JCT	CYPRESS	获取价格	Dual-Port SRAM, 2KX8, 45ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C136-45JI	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C136-45JIR	CYPRESS	获取价格	Multi-Port SRAM, 2KX8, 45ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C136-45JIT	CYPRESS	获取价格	Dual-Port SRAM, 2KX8, 45ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C136-45JXC	CYPRESS	获取价格	Dual-Port SRAM, 2KX8, 45ns, CMOS, PQCC52, PLASTIC, LEAD FREE, LCC-52
CY7C136-45LC	ETC	获取价格	x8 Dual-Port SRAM
CY7C136-45LMB	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C136-45LMBT	CYPRESS	获取价格	Dual-Port SRAM, 2KX8, 45ns, CMOS, LCC-52

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