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CY7C1364C-166AJXI PDF预览

CY7C1364C-166AJXI

更新时间: 2024-09-29 05:19:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
18页 396K
描述
9-Mbit (256K x 32) Pipelined Sync SRAM

CY7C1364C-166AJXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP100,.63X.87针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.62
最长访问时间:3.5 ns其他特性:PIPELINED ARCHITECTURE
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e3长度:20 mm
内存密度:8388608 bit内存集成电路类型:CACHE SRAM
内存宽度:32湿度敏感等级:3
功能数量:1端子数量:100
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:2.5/3.3,3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.04 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.18 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mm

CY7C1364C-166AJXI 数据手册

 浏览型号CY7C1364C-166AJXI的Datasheet PDF文件第2页浏览型号CY7C1364C-166AJXI的Datasheet PDF文件第3页浏览型号CY7C1364C-166AJXI的Datasheet PDF文件第4页浏览型号CY7C1364C-166AJXI的Datasheet PDF文件第5页浏览型号CY7C1364C-166AJXI的Datasheet PDF文件第6页浏览型号CY7C1364C-166AJXI的Datasheet PDF文件第7页 
CY7C1364C  
9-Mbit (256K x 32) Pipelined Sync SRAM  
Features  
Functional Description[1]  
• Registered inputs and outputs for pipelined operation  
• 256K × 32 common I/O architecture  
The CY7C1364C SRAM integrates 256K x 32 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst  
Control inputs (ADSC, ADSP, and ADV), Write Enables  
(BW[A:D], and BWE), and Global Write (GW). Asynchronous  
inputs include the Output Enable (OE) and the ZZ pin.  
• 3.3V core power supply (VDD  
)
• 2.5V/3.3V I/O power supply (VDDQ  
)
• Fast clock-to-output times  
— 2.8 ns (for 250-MHz device)  
• Provide high-performance 3-1-1-1 access rate  
• User-selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
controlled by the Byte Write control inputs. GW when active  
• Available in JEDEC-standard lead-free 100-Pin TQFP  
package  
• TQFP Available with 3-Chip Enable and 2-Chip Enable  
• “ZZ” Sleep Mode Option  
causes all bytes to be written.  
LOW  
The CY7C1364C operates from a +3.3V core power supply  
while all outputs may operate with either a +2.5 or +3.3V  
supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Logic Block Diagram-CY7C1364C (256K x 32)  
A0, A1, A  
ADDRESS  
REGISTER  
2
A[1:0]  
MODE  
Q1  
ADV  
CLK  
BURST  
COUNTER  
AND  
LOGIC  
CLR  
Q0  
ADSC  
ADSP  
DQ  
BYTE  
WRITE REGISTER  
D
DQ  
BYTE  
WRITE DRIVER  
D
BW  
D
DQ  
BYTE  
C
DQ  
BYTE  
C
BW  
C
OUTPUT  
BUFFERS  
WRITE DRIVER  
OUTPUT  
REGISTERS  
WRITE REGISTER  
MEMORY  
ARRAY  
SENSE  
AMPS  
DQ s  
DQ  
B
E
DQ  
B
BYTE  
WRITE DRIVER  
BYTE  
WRITE REGISTER  
BW  
BW  
B
A
DQ  
A
DQ  
A
BYTE  
WRITE DRIVER  
BYTE  
WRITE REGISTER  
BWE  
INPUT  
REGISTERS  
GW  
ENABLE  
REGISTER  
PIPELINED  
ENABLE  
CE  
CE  
CE  
1
2
3
OE  
SLEEP  
CONTROL  
ZZ  
Notes:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE is not available on 2 Chip Enable TQFP package.  
3
Cypress Semiconductor Corporation  
Document #: 38-05689 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 14, 2006  
[+] Feedback  

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