CY7C1364C-166AXC

更新时间： 2024-11-16 05:19:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
18页	396K
描述
9-Mbit (256K x 32) Pipelined Sync SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1364C-166AXC 数据手册

CY7C1364C

9-Mbit (256K x 32) Pipelined Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• 256K × 32 common I/O architecture

The CY7C1364C SRAM integrates 256K x 32 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃^[2]), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW_[A:D], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

• 3.3V core power supply (V_DD

)

• 2.5V/3.3V I/O power supply (V_DDQ

)

• Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the Byte Write control inputs. GW when active

• Available in JEDEC-standard lead-free 100-Pin TQFP

package

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• “ZZ” Sleep Mode Option

causes all bytes to be written.

LOW

The CY7C1364C operates from a +3.3V core power supply

while all outputs may operate with either a +2.5 or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram-CY7C1364C (256K x 32)

A0, A1, A

ADDRESS

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND

LOGIC

CLR

ADSC

ADSP

BYTE

WRITE REGISTER

BYTE

WRITE DRIVER

BYTE

OUTPUT

BUFFERS

WRITE DRIVER

OUTPUT

REGISTERS

WRITE REGISTER

MEMORY

ARRAY

SENSE

AMPS

DQ s

BYTE

WRITE DRIVER

BYTE

WRITE REGISTER

BYTE

WRITE DRIVER

BYTE

WRITE REGISTER

BWE

INPUT

REGISTERS

ENABLE

PIPELINED

ENABLE

SLEEP

CONTROL

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is not available on 2 Chip Enable TQFP package.

Cypress Semiconductor Corporation

Document #: 38-05689 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

[+] Feedback

12 3 4 5 6 7...18

中文翻译

下载PDF

与CY7C1364C-166AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1364C-166AXCT	CYPRESS	获取价格	Cache SRAM, 256KX32, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026,
CY7C1364C-166AXI	CYPRESS	获取价格	9-Mbit (256K x 32) Pipelined Sync SRAM
CY7C1364C-200AJXC	CYPRESS	获取价格	9-Mbit (256K x 32) Pipelined Sync SRAM
CY7C1364C-200AJXI	CYPRESS	获取价格	9-Mbit (256K x 32) Pipelined Sync SRAM
CY7C1364C-200AXC	CYPRESS	获取价格	9-Mbit (256K x 32) Pipelined Sync SRAM
CY7C1364C-200AXI	CYPRESS	获取价格	9-Mbit (256K x 32) Pipelined Sync SRAM
CY7C1364C-250AJXC	CYPRESS	获取价格	9-Mbit (256K x 32) Pipelined Sync SRAM
CY7C1364C-250AJXI	CYPRESS	获取价格	9-Mbit (256K x 32) Pipelined Sync SRAM
CY7C1364C-250AXC	CYPRESS	获取价格	9-Mbit (256K x 32) Pipelined Sync SRAM
CY7C1364C-250AXI	CYPRESS	获取价格	9-Mbit (256K x 32) Pipelined Sync SRAM

与CY7C1364C-166AXC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

13
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

7
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

35
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1364C-166AXC

CY7C1364C-166AXC 数据手册

与CY7C1364C-166AXC相关器件

与CY7C1364C-166AXC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1364C-166AXC

CY7C1364C-166AXC 数据手册

与CY7C1364C-166AXC相关器件

与CY7C1364C-166AXC相关文章

您还可以找

您在本页遇到什么问题？