Datasheet > CY7C1365B

CY7C1365B

更新时间： 2024-11-16 05:19:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
16页	328K
描述
9-Mb (265K x 32) Flow-Through Sync SRAM

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CY7C1365B 数据手册

CY7C1365B

9-Mb (265K x 32) Flow-Through Sync SRAM

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

Features

• 256K x 32 common I/O

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

• 3.3V –5% and +10% core power supply (V_DD

)

• 3.3V I/O supply (V_DDQ

)

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

— 7.5 ns (117-MHz version)

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

Control inputs (

), Write Enables

). Asynchronous

and

ADV

ADSC ADSP

(

and

), and Global Write (

BW_[A:D]

BWE

(

)

and the ZZ pin

• Provide high-performance 2-1-1-1 access rate

nputs include the Output Enable

• User-selectable burst counter supporting Intel^

The CY7C1365B allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP) or the cache Controller

Address Strobe (ADSC) inputs. Address advancement is

controlled by the Address Advancement (ADV) input.

Pentium^interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Supports 3.3V I/O level

Addresses and Chip Enables are registered at rising edge of

• Offered in JEDEC-standard 100-pin TQFP package

— Both 2 and 3 Chip Enable Options for TQFP

• “ZZ” Sleep Mode option

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

ADV

Functional Description^[1]

The CY7C1365B operates from a +3.3V core power supply

while all outputs may operate with a +3.3V supply. All inputs

and outputs are JEDEC-standard JESD8-5-compatible.

The CY7C1365B is a 256K x 32 synchronous cache RAM

designed to interface with high-speed microprocessors with

Logic Block Diagram

ADDRESS

A0, A1, A

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND LOGIC

CLR

ADSC

ADSP

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

OUTPUT

BUFFERS

DQs

WRITE REGISTER

MEMORY

ARRAY

SENSE

AMPS

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

BWE

WRITE REGISTER

INPUT

REGISTERS

ENABLE

CE1

CE2

CE3

SLEEP

CONTROL

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com

2. is not available on 2 Chip Enable TQFP package.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05433 Rev. **

Revised January 29, 2003

12 3 4 5 6 7...16

中文翻译

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与CY7C1365B相关器件

型号	品牌	获取价格	描述	数据表
CY7C1365B-117AC	CYPRESS	获取价格	9-Mb (265K x 32) Flow-Through Sync SRAM
CY7C1365B-117AJC	CYPRESS	获取价格	9-Mb (265K x 32) Flow-Through Sync SRAM
CY7C1365C	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-100AJXC	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-100AJXI	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-100AXC	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-100AXI	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-133AJXC	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-133AJXI	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-133AXC	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM

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