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CY7C1365C-133AJXI PDF预览

CY7C1365C-133AJXI

更新时间: 2024-11-16 03:57:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
18页 397K
描述
9-Mbit (256K x 32) Flow-Through Sync SRAM

CY7C1365C-133AJXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP100,.63X.87针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.67
最长访问时间:6.5 ns其他特性:FLOW-THROUGH ARCHITECTURE
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e3长度:20 mm
内存密度:8388608 bit内存集成电路类型:CACHE SRAM
内存宽度:32湿度敏感等级:3
功能数量:1端子数量:100
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:2.5/3.3,3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.04 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.25 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

CY7C1365C-133AJXI 数据手册

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CY7C1365C  
9-Mbit (256K x 32) Flow-Through Sync SRAM  
Features  
Functional Description[1]  
• 256K x 32 common I/O  
The CY7C1365C is a 256K x 32 synchronous cache RAM  
designed to interface with high-speed microprocessors with  
minimum glue logic. Maximum access delay from clock rise is  
• 3.3V core power supply (VDD  
)
• 2.5V/3.3V I/O power supply (VDDQ  
• Fast clock-to-output times  
— 6.5 ns (133-MHz version)  
)
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the  
first address in a burst and increments the address automati-  
cally for the rest of the burst access. All synchronous inputs  
are gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst  
Control inputs (ADSC, ADSP, and ADV), Write Enables  
(BW[A:D], and BWE), and Global Write (GW). Asynchronous  
• Provide high-performance 2-1-1-1 access rate  
• User-selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
inputs include the Output Enable (OE) and the ZZ pin  
.
• Asynchronous output enable  
The CY7C1365C allows either interleaved or linear burst  
sequences, selected by the MODE input pin. A HIGH selects  
an interleaved burst sequence, while a LOW selects a linear  
burst sequence. Burst accesses can be initiated with the  
Processor Address Strobe (ADSP) or the cache Controller  
Address Strobe (ADSC) inputs. Address advancement is  
controlled by the Address Advancement (ADV) input.  
• Supports 3.3V I/O level  
• Available in JEDEC-standard lead-free 100-Pin TQFP  
package  
• TQFP Available with 3-Chip Enable and 2-Chip Enable  
• “ZZ” Sleep Mode option  
Addresses and Chip Enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
The CY7C1365C operates from a +3.3V core power supply  
while all outputs may operate with either a +2.5 or +3.3V  
supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum Standby Current  
250  
40  
180  
mA  
mA  
40  
Notes:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. is not available on 2 Chip Enable TQFP package.  
CE  
3
Cypress Semiconductor Corporation  
Document #: 38-05690 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 14, 2006  
[+] Feedback  

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