Datasheet > CY7C1365C

CY7C1365C

更新时间： 2024-11-16 05:19:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
18页	397K
描述
9-Mbit (256K x 32) Flow-Through Sync SRAM

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CY7C1365C 数据手册

CY7C1365C

9-Mbit (256K x 32) Flow-Through Sync SRAM

Features

Functional Description^[1]

• 256K x 32 common I/O

The CY7C1365C is a 256K x 32 synchronous cache RAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

• 3.3V core power supply (V_DD

)

• 2.5V/3.3V I/O power supply (V_DDQ

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

)

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃^[2]), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW[A:D], and BWE), and Global Write (GW). Asynchronous

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

inputs include the Output Enable (OE) and the ZZ pin

• Asynchronous output enable

The CY7C1365C allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP) or the cache Controller

Address Strobe (ADSC) inputs. Address advancement is

controlled by the Address Advancement (ADV) input.

• Supports 3.3V I/O level

• Available in JEDEC-standard lead-free 100-Pin TQFP

package

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• “ZZ” Sleep Mode option

Addresses and Chip Enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1365C operates from a +3.3V core power supply

while all outputs may operate with either a +2.5 or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum Standby Current

250

180

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. is not available on 2 Chip Enable TQFP package.

Cypress Semiconductor Corporation

Document #: 38-05690 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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与CY7C1365C相关器件

型号	品牌	获取价格	描述	数据表
CY7C1365C-100AJXC	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-100AJXI	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-100AXC	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-100AXI	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-133AJXC	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-133AJXI	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-133AXC	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C-133AXCT	CYPRESS	获取价格	Cache SRAM, 256KX32, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026,
CY7C1365C-133AXI	CYPRESS	获取价格	9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365CV33	CYPRESS	获取价格	9-Mbit (256 K Ã 32) Flow-Through Sync SRAM

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