Datasheet > 存储 > SRAM> CY7C1363C-133BGI

CY7C1363C-133BGI

更新时间： 2024-11-16 05:19:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	562K
描述
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

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CY7C1363C-133BGI 数据手册

CY7C1361C

CY7C1363C

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Features

Functional Description^[1]

• Supports 100, 133-MHz bus operations

• Supports 100-MHz bus operations (Automotive)

• 256K × 36/512K × 18 common I/O

The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36/512K x 18

Synchronous Flow-through SRAMs, respectively designed to

interface with high-speed microprocessors with minimum glue

logic. Maximum access delay from clock rise is 6.5 ns

(133-MHz version). A 2-bit on-chip counter captures the first

address in a burst and increments the address automatically

for the rest of the burst access. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃^[2]), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables (BW_x,

and BWE), and Global Write (GW). Asynchronous inputs

include the Output Enable (OE) and the ZZ pin.

• 3.3V –5% and +10% core power supply (V_DD

)

• 2.5V or 3.3V I/O power supply (V_DDQ

)

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

The CY7C1361C/CY7C1363C allows either interleaved or

linear burst sequences, selected by the MODE input pin. A

HIGH selects an interleaved burst sequence, while a LOW

selects a linear burst sequence. Burst accesses can be

initiated with the Processor Address Strobe (ADSP) or the

cache Controller Address Strobe (ADSC) inputs. Address

advancement is controlled by the Address Advancement

(ADV) input.

• Asynchronous output enable

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• IEEE 1149.1 JTAG-Compatible Boundary Scan

•“ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1361C/CY7C1363C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

250

180

Maximum CMOS Standby Current

Comm/Ind’l

Automotive

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.

Cypress Semiconductor Corporation

Document #: 38-05541 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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与CY7C1363C-133BGI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1363C-133BGXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133BGXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133BZC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133BZI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133BZXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133BZXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363D	CYPRESS	获取价格	9-Mbit (512 K x 18) Flow-Through SRAM
CY7C1363D-133AXI	CYPRESS	获取价格	9-Mbit (512 K x 18) Flow-Through SRAM
CY7C136-45JC	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C136-45JCR	CYPRESS	获取价格	暂无描述

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