Datasheet > CY7C1363C-117BGC

CY7C1363C-117BGC

更新时间： 2024-09-28 09:44:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	476K
描述
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

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CY7C1363C-117BGC 数据手册

CY7C1361C

CY7C1363C

PRELIMINARY

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Features

Functional Description^[1]

• Supports 133-MHz bus operations

• 256K × 36/512K × 18 common I/O

• 3.3V –5% and +10% core power supply (V_DD

The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x

18 Synchronous Flowthrough SRAMs, respectively designed

to interface with high-speed microprocessors with minimum

glue logic. Maximum access delay from clock rise is 6.5 ns

(133-MHz version). A 2-bit on-chip counter captures the first

address in a burst and increments the address automatically

for the rest of the burst access. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

)

• 2.5V or 3.3V I/O supply (V_DDQ

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

— 7.5 ns (117-MHz version)

— 8.5 ns (100-MHz version)

)

addresses, all data inputs, address-pipelining Chip Enable

[2]

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

Control inputs (

), Write Enables

(

ADV

BW_x

and

• Provide high-performance 2-1-1-1 access rate

ADSC ADSP

), and Global Write (

BWE

). Asynchronous

and

inputs

• User-selectable burst counter supporting Intel^

(

)

and the ZZ pin

include the Output Enable

Pentium^interleaved or linear burst sequences

The CY7C1361C/CY7C1363C allows either interleaved or

linear burst sequences, selected by the MODE input pin. A

HIGH selects an interleaved burst sequence, while a LOW

selects a linear burst sequence. Burst accesses can be

initiated with the Processor Address Strobe (ADSP) or the

cache Controller Address Strobe (ADSC) inputs. Address

advancement is controlled by the Address Advancement

(ADV) input.

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• AvailableinLead-Free100TQFP,119BGAand165fBGA

packages Both 2 and 3 Chip Enable Options for TQFP

• IEEE 1149.1 compatible JTAG Boundary Scan for BGA

and fBGA packages

•“ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

ADV

The CY7C1361C/CY7C1363C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

133 MHz

117 MHz

7.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

6.5

250

220

180

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is for A version of TQFP ( 3 Chip Enable Option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05541 Rev. *A

Revised October 5, 2004

12 3 4 5 6 7...30

中文翻译

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与CY7C1363C-117BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1363C-117BGI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-117BZC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-117BZI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133AJXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133AJXCT	CYPRESS	获取价格	Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026,
CY7C1363C-133AJXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133AJXIT	CYPRESS	获取价格	Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026,
CY7C1363C-133AXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363C-133AXCT	CYPRESS	获取价格	Standard SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-02
CY7C1363C-133AXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

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