Datasheet > 存储 > SRAM> CY7C1354BV25-225

CY7C1354BV25-225

更新时间： 2024-09-16 22:04:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
27页	517K
描述
256K x 36/512K x 18 Pipelined SRAM with NoBL⑩ Architecture

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中文翻译

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CY7C1354BV25-225 数据手册

CY7C1354BV25

CY7C1356BV25

256K x 36/512K x 18 Pipelined SRAM with

NoBL™ Architecture

Features

Functional Description

• Pin-compatible and functionally equivalent to ZBT™

• Supports 225-MHz bus operations with zero wait states

— Available speed grades are 225, 200 and 166 MHz

The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x

36 and 512K x 18 Synchronous pipelined burst SRAMs with

No Bus Latency™ (NoBL) logic, respectively. They are

designed to support unlimited true back-to-back Read/Write

operations with no wait states. The CY7C1354BV25 and

CY7C1356BV25 are equipped with the advanced (NoBL) logic

required to enable consecutive Read/Write operations with

data being transferred on every clock cycle. This feature

dramatically improves the throughput of data in systems that

require frequent Write/Read transitions. The CY7C1354BV25

and CY7C1356BV25 are pin compatible and functionally

equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BW_a–BW_dfor CY7C1354BV25 and BW_a–BW_bfor

CY7C1356BV25) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 2.5V power supply

• Fast clock-to-output times

— 2.8 ns (for 225-MHz device)

— 3.2ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Available in 100 TQFP, 119 BGA, and 165 fBGA packag-

• IEEE 1149.1 JTAG Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Logic Block Diagram-CY7C1354BV25 (256K x 36)

ADDRESS

A0, A1, A

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

DQP

WRITE

DRIVERS

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05292 Rev. *E

Revised August 10, 2004

12 3 4 5 6 7...27

中文翻译

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与CY7C1354BV25-225相关器件

型号	品牌	获取价格	描述	数据表
CY7C1354BV25-225BGC	CYPRESS	获取价格	ZBT SRAM, 256KX36, 2.8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1354C	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C_06	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C_11	CYPRESS	获取价格	9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM
CY7C1354C-166AXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166AXC	INFINEON	获取价格	Synchronous SRAM
CY7C1354C-166AXCT	CYPRESS	获取价格	ZBT SRAM, 256KX36, 3.5ns, CMOS, PQFP100,
CY7C1354C-166AXCT	INFINEON	获取价格	Synchronous SRAM
CY7C1354C-166AXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166AXI	INFINEON	获取价格	Synchronous SRAM

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