5秒后页面跳转
捷配首页

Datasheet > CY7C1354C-166AXIT
CY7C1354C-166AXIT PDF预览

CY7C1354C-166AXIT

更新时间： 2024-11-27 18:58:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
36页 3289K
描述
ZBT SRAM, 256KX36, 3.5ns, CMOS, PQFP100,

阅读下载

中文翻译

获取价格

CY7C1354C-166AXIT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：QFP, QFP100,.63X.87
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.77
最长访问时间：3.5 ns最大时钟频率 (fCLK)：166 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e4内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL电源：2.5/3.3,3.3 V
认证状态：Not Qualified最大待机电流：0.04 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.18 mA表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：QUAD
Base Number Matches：1

CY7C1354C-166AXIT 数据手册

 浏览型号CY7C1354C-166AXIT的Datasheet PDF文件第2页浏览型号CY7C1354C-166AXIT的Datasheet PDF文件第3页浏览型号CY7C1354C-166AXIT的Datasheet PDF文件第4页浏览型号CY7C1354C-166AXIT的Datasheet PDF文件第5页浏览型号CY7C1354C-166AXIT的Datasheet PDF文件第6页浏览型号CY7C1354C-166AXIT的Datasheet PDF文件第7页 
CY7C1354C  
CY7C1356C  
9-Mbit (256K × 36/512K × 18)  
Pipelined SRAM with NoBL™ Architecture  
9-Mbit (256K  
× 36/512K × 18) Pipelined SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ Pin-compatible and functionally equivalent to ZBT  
The  
CY7C1354C/CY7C1356C[1]  
are  
3.3 V,  
256K × 36/512K × 18 synchronous pipelined burst SRAMs with  
No Bus Latency™ (NoBL™) logic, respectively. They are  
designed to support unlimited true back-to-back read/write  
operations with no wait states. The CY7C1354C/CY7C1356C  
are equipped with the advanced (NoBL) logic required to enable  
consecutive read/write operations with data being transferred on  
every clock cycle. This feature greatly improves the throughput  
of data in systems that require frequent write/read transitions.  
The CY7C1354C/CY7C1356C are pin compatible and  
functionally equivalent to ZBT devices.  
■ Supports 250 MHz bus operations with zero wait states  
❐ Available speed grades are 250, 200, and 166 MHz  
■ Internally self-timed output buffer control to eliminate the need  
to use asynchronous OE  
■ Fully registered (inputs and outputs) for pipelined operation  
■ Byte write capability  
■ Single 3.3 V power supply (VDD  
)
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the clock enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle.  
■ 3.3 V or 2.5 V I/O power supply (VDDQ  
)
■ Fast clock-to-output times  
❐ 2.8 ns (for 250 MHz device)  
■ Clock enable (CEN) pin to suspend operation  
■ Synchronous self-timed writes  
Write operations are controlled by the byte write selects  
(BWa–BWd for CY7C1354C and BWa–BWb for CY7C1356C)  
and a write enable (WE) input. All writes are conducted with  
on-chip synchronous self-timed write circuitry.  
■ Available in Pb-free 100-pin TQFP package, Pb-free, and non  
Pb-free 119-ball BGA package and 165-ball FBGA package  
■ IEEE 1149.1 JTAG-compatible boundary scan  
■ Burst capability – linear or interleaved burst order  
■ “ZZ” sleep mode option and stop clock option  
Three synchronous chip enables (CE1, CE2, CE3) and an  
asynchronous output enable (OE) provide for easy bank  
selection and output tristate control. To avoid bus contention, the  
output drivers are synchronously tristated during the data portion  
of a write sequence.  
For a complete list of related documentation, click here.  
Selection Guide  
Description  
Maximum access time  
250 MHz  
2.8  
200 MHz  
3.2  
166 MHz Unit  
3.5  
180  
40  
ns  
Maximum operating current  
250  
220  
mA  
mA  
Maximum CMOS standby current  
40  
40  
Note  
1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document Number: 38-05538 Rev. *S  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 4, 2016  
 
 
 
1234567...36

中文翻译

下载PDF

CY7C1354C-166AXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1354C-166AXI CYPRESS

类似代替

 9-Mbit (256K x 36/512K x 18) Pipelined SRAM w

与CY7C1354C-166AXIT相关器件

型号 品牌 获取价格 描述 数据表
CY7C1354C-166BGC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BGCT CYPRESS

获取价格

 		暂无描述
CY7C1354C-166BGI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BGIT CYPRESS

获取价格

 		ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA119, (14 X 22 X 2.4) MM, PLASTIC, BGA-119
CY7C1354C-166BGXC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BGXI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BZC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BZCT CYPRESS

获取价格

 		ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA165
CY7C1354C-166BZI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BZXC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w

与CY7C1354C-166AXIT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证