Datasheet > 存储 > SRAM> CY7C1354C-250AXI

CY7C1354C-250AXI

更新时间： 2024-11-07 05:19:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	511K
描述
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1354C-250AXI 数据手册

CY7C1354C

CY7C1356C

9-Mbit (256K x 36/512K x 18)

Pipelined SRAM with NoBL™ Architecture

Functional Description^[1]

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200, and 166 MHz

The CY7C1354C and CY7C1356C are 3.3V, 256K x 36 and

512K x 18 Synchronous pipelined burst SRAMs with No Bus

Latency™ (NoBL™) logic, respectively. They are designed to

support unlimited true back-to-back Read/Write operations

with no wait states. The CY7C1354C and CY7C1356C are

equipped with the advanced (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent

Write/Read transitions. The CY7C1354C and CY7C1356C are

pin compatible and functionally equivalent to ZBT devices.

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 3.3V power supply (V_DD

)

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

• 3.3V or 2.5V I/O power supply (V_DDQ

)

• Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

Write operations are controlled by the Byte Write Selects

(BW_a–BW_dfor CY7C1354C and BW_a–BW_bfor CY7C1356C)

and a Write Enable (WE) input. All writes are conducted with

on-chip synchronous self-timed write circuitry.

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability–linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Logic Block Diagram–CY7C1354C (256K x 36)

ADDRESS

A0, A1, A

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

DQP

WRITE

DRIVERS

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05538 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

[+] Feedback

12 3 4 5 6 7...28

中文翻译

下载PDF

与CY7C1354C-250AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1354C-250BGC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-250BGI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-250BGXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-250BGXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-250BZC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-250BZI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-250BZXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-250BZXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354CV25	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354CV25_06	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w

与CY7C1354C-250AXI相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

16
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

13
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

37
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

34

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1354C-250AXI

CY7C1354C-250AXI 数据手册

与CY7C1354C-250AXI相关器件

与CY7C1354C-250AXI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1354C-250AXI

CY7C1354C-250AXI 数据手册

与CY7C1354C-250AXI相关器件

与CY7C1354C-250AXI相关文章

您还可以找

您在本页遇到什么问题？