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CY7C1354CV25

更新时间： 2024-11-07 05:19:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
28页 488K
描述
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture

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CY7C1354CV25 数据手册

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CY7C1354CV25  
CY7C1356CV25  
9-Mbit (256K x 36/512K x 18)  
Pipelined SRAM with NoBL™ Architecture  
Functional Description[1]  
Features  
• Pin-compatible with and functionally equivalent to  
ZBT™  
The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x  
36 and 512K x 18 Synchronous pipelined burst SRAMs with  
No Bus Latency™ (NoBL™) logic, respectively. They are  
designed to support unlimited true back-to-back Read/Write  
operations with no wait states. The CY7C1354CV25 and  
CY7C1356CV25 are equipped with the advanced (NoBL) logic  
required to enable consecutive Read/Write operations with  
data being transferred on every clock cycle. This feature  
dramatically improves the throughput of data in systems that  
require frequent Write/Read transitions. The CY7C1354CV25  
and CY7C1356CV25 are pin-compatible with and functionally  
equivalent to ZBT devices.  
• Supports 250-MHz bus operations with zero wait states  
• Available speed grades are 250, 200, and 166 MHz  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
• Single 2.5V power supply (VDD  
• Fast clock-to-output times  
— 2.8 ns (for 250-MHz device)  
)
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle.  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• Available in lead-free 100-Pin TQFP package, lead-free  
and non lead-free 119-Ball BGA package and 165-Ball  
FBGA package  
Write operations are controlled by the Byte Write Selects  
(BWa–BWd for CY7C1354CV25 and BWa–BWb for  
CY7C1356CV25) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• Burst capability–linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
Logic Block Diagram–CY7C1354CV25 (256K x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05537 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 14, 2006  
[+] Feedback  
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