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CY7C1354C-166BZCT PDF预览

CY7C1354C-166BZCT

更新时间： 2024-09-17 21:14:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
30页 752K
描述
ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA165

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CY7C1354C-166BZCT 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：ObsoleteReach Compliance Code：unknown
风险等级：5.86最长访问时间：3.5 ns
最大时钟频率 (fCLK)：166 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：36
端子数量：165字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
电源：2.5/3.3,3.3 V认证状态：Not Qualified
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.18 mA
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
Base Number Matches：1

CY7C1354C-166BZCT 数据手册

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CY7C1354C, CY7C1356C  
9-Mbit (256K x 36/512K x 18)  
Pipelined SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ Pin-compatible and Functionally equivalent to ZBT  
The CY7C1354C and CY7C1356C[1] are 3.3V, 256K x 36 and  
512K x 18 Synchronous pipelined burst SRAMs with No Bus  
Latency™ (NoBL™) logic, respectively. They are designed to  
support unlimited true back-to-back read/write operations with  
no wait states. The CY7C1354C and CY7C1356C are  
equipped with the advanced (NoBL) logic required to enable  
consecutive read/write operations with data being transferred  
on every clock cycle. This feature greatly improves the  
throughput of data in systems that require frequent write/read  
transitions. The CY7C1354C and CY7C1356C are pin  
compatible and functionally equivalent to ZBT devices.  
■ Supports 250 MHz Bus Operations with Zero Wait States  
❐ Available speed grades are 250, 200, and 166 MHz  
■ Internally Self-timed Output Buffer Control to eliminate the  
need to use Asynchronous OE  
■ Fully Registered (Inputs and Outputs) for Pipelined  
Operation  
■ Byte Write capability  
■ Single 3.3V Power Supply (VDD  
)
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle.  
■ 3.3V or 2.5V I/O Power Supply (VDDQ  
)
■ Fast Clock-to-output Times  
❐ 2.8 ns (for 250 MHz device)  
■ Clock Enable (CEN) Pin to suspend Operation  
■ Synchronous Self-timed Writes  
Write operations are controlled by the Byte Write Selects  
(BWa–BWd for CY7C1354C and BWa–BWb for CY7C1356C)  
and a Write Enable (WE) input. All writes are conducted with  
on-chip synchronous self-timed write circuitry.  
■ Available in Pb-free 100-Pin TQFP Package, Pb-free, and  
non Pb-free 119-Ball BGA Package and 165-Ball FBGA  
Package  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tristate control. To avoid bus contention,  
the output drivers are synchronously tristated during the data  
portion of a write sequence.  
■ IEEE 1149.1 JTAG-Compatible Boundary Scan  
■ Burst Capability – Linear or Interleaved Burst Order  
■ “ZZ” Sleep Mode option and Stop Clock option  
Logic Block Diagram–CY7C1354C (256K x 36)  
ADDRESS  
REGISTER  
A0, A1,  
A
0
A1  
A0  
A1'  
Q1  
Q0  
D1  
D0  
BURST  
LOGIC  
A0'  
MODE  
ADV/LD  
CLK  
CEN  
C
C
WRITE ADDRESS  
REGISTER  
WRITE ADDRESS  
REGISTER 2  
1
O
U
T
O
U
T
S
E
D
A
T
P
U
T
N
S
P
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
F
E
R
S
S
T
E
E
R
I
DQ s  
DQ P  
DQ P  
DQ P  
DQ P  
WRITE  
DRIVERS  
BW  
a
a
b
c
A
M
P
BW  
BW  
BW  
b
c
S
T
E
R
S
d
d
S
WE  
E
E
N
G
INPUT  
REGISTER  
INPUT  
REGISTER 0  
E
E
1
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Note  
1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05538 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 25, 2009  
[+] Feedback  
 
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