Datasheet > CY7C1354C-166AXIT

CY7C1354C-166AXIT

更新时间： 2024-11-26 15:17:59

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
36页	1096K
描述
Synchronous SRAM

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数据手册

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CY7C1354C

CY7C1356C

9-Mbit (256K × 36/512K × 18)

Pipelined SRAM with NoBL™ Architecture

9-Mbit (256K

× 36/512K × 18) Pipelined SRAM with NoBL™ Architecture

Features

Functional Description

■ Pin-compatible and functionally equivalent to ZBT

The

CY7C1354C/CY7C1356C^[1]

are

3.3 V,

256K × 36/512K × 18 synchronous pipelined burst SRAMs with

No Bus Latency™ (NoBL™) logic, respectively. They are

designed to support unlimited true back-to-back read/write

operations with no wait states. The CY7C1354C/CY7C1356C

are equipped with the advanced (NoBL) logic required to enable

consecutive read/write operations with data being transferred on

every clock cycle. This feature greatly improves the throughput

of data in systems that require frequent write/read transitions.

The CY7C1354C/CY7C1356C are pin compatible and

functionally equivalent to ZBT devices.

■ Supports 250 MHz bus operations with zero wait states

❐ Available speed grades are 250, 200, and 166 MHz

■ Internally self-timed output buffer control to eliminate the need

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte write capability

■ Single 3.3 V power supply (V_DD

)

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the clock enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle.

■ 3.3 V or 2.5 V I/O power supply (V_DDQ

)

■ Fast clock-to-output times

❐ 2.8 ns (for 250 MHz device)

■ Clock enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

Write operations are controlled by the byte write selects

(BW_a–BW_dfor CY7C1354C and BW_a–BW_bfor CY7C1356C)

and a write enable (WE) input. All writes are conducted with

on-chip synchronous self-timed write circuitry.

■ Available in Pb-free 100-pin TQFP package, Pb-free, and non

Pb-free 119-ball BGA package and 165-ball FBGA package

■ IEEE 1149.1 JTAG-compatible boundary scan

■ Burst capability – linear or interleaved burst order

■ “ZZ” sleep mode option and stop clock option

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide for easy bank

selection and output tristate control. To avoid bus contention, the

output drivers are synchronously tristated during the data portion

of a write sequence.

For a complete list of related documentation, click here.

Selection Guide

Description

Maximum access time

250 MHz

2.8

200 MHz

3.2

166 MHz Unit

3.5

180

Maximum operating current

250

220

Maximum CMOS standby current

Note

1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document Number: 38-05538 Rev. *T

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 9, 2018

12 3 4 5 6 7...36

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与CY7C1354C-166AXIT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1354C-166BGC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BGCT	CYPRESS	获取价格	暂无描述
CY7C1354C-166BGI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BGIT	CYPRESS	获取价格	ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA119, (14 X 22 X 2.4) MM, PLASTIC, BGA-119
CY7C1354C-166BGXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BGXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BZC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BZCT	CYPRESS	获取价格	ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA165
CY7C1354C-166BZI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1354C-166BZXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM w

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