CY7C1298A-66NC

更新时间： 2024-10-01 03:05:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		脉冲
页数	文件大小	规格书
12页	161K
描述
64K x 18 Synchronous Burst RAM Pipelined Output

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CY7C1298A-66NC 数据手册

298A

CY7C1298A/

GVT7164C18

64K x 18 Synchronous Burst RAM

Pipelined Output

The CY7C1298A/GVT7164C18 SRAM integrates 65536x18

SRAM cells with advanced synchronous peripheral circuitry

and a 2-bit counter for internal burst operation. All synchro-

nous inputs are gated by registers controlled by a posi-

tive-edge-triggered Clock input (CLK). The synchronous in-

puts include all addresses, all data inputs, address-pipelining

Chip Enable (CE), depth-expansion Chip Enables (CE2 and

CE2), burst control inputs (ADSC, ADSP, and ADV), Write En-

ables (WEL, WEH, and BWE), and Global Write (GW).

Features

• Fast access times: 5, 6, 7, and 8 ns

• Fast clock speed: 100, 83, 66, and 50 MHz

• Provide high-performance 3-1-1-1 access rate

• Fast OE access times: 5 and 6 ns

• Optimal for performance (two cycle chip deselect,

depth expansion without wait state)

• Single +3.3V –5 to +10% power supply

• 5V tolerant inputs except I/Os

• Clamp diodes to V_SSQat all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

Asynchronous inputs include the Output Enable (OE) and

Burst Mode Control (MODE). The data outputs (Q), enabled

by OE, are also asynchronous.

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the burst advance pin (ADV).

• Three chip enables for depth expansion and address

pipeline

• Address, control, input, and output pipeline registers

• Internally self-timed Write Cycle

• Write pass-through capability

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down for portable applications

• High-density, high-speed packages

Address, data inputs, and write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs. Indi-

vidual byte write allows individual byte to be written. WEL con-

trols DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and

DQP2. WEL and WEH can be active only with BWE being

LOW. GW being LOW causes all bytes to be written. This de-

vice also incorporates Write pass-through capability and pipe-

lined enable circuit for better system performance.

• Low capacitive bus loading

• High 30-pF output drive capability at rated access time

The CY7C1298A/GVT7164C18 operates from a +3.3V power

supply. All inputs and outputs are TTL-compatible. The device

is ideally suited for 486, Pentium®, 680x0, and PowerPC™

systems and for systems that are benefited from a wide syn-

chronous data bus.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced dou-

ble-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high valued

resistors.

Selection Guide

7C1298A-100

7164C18-5

7C1298A-83

7164C18-6

7C1298A-66

7164C18-7

7C1298A-50

7164C18-8

Maximum Access Time (ns)

360

315

270

225

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Pentium is a registered trademark of Intel Corporation.

PowerPC is a trademark of International Business Machines, Inc.

Cypress Semiconductor Corporation

Document #: 38-05194 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised January 19, 2003

12 3 4 5 6 7...12

中文翻译

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与CY7C1298A-66NC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1298A-83NC	CYPRESS	获取价格	64K x 18 Synchronous Burst RAM Pipelined Output
CY7C1298F	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298F-133AC	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298F-133ACT	CYPRESS	获取价格	Standard SRAM, 64KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1298F-133AXC	CYPRESS	获取价格	Standard SRAM, 64KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1298H	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H-100AXC	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H-100AXI	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H-133AXC	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H-133AXI	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM

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