Datasheet > CY7C130_12

CY7C130_12

更新时间： 2024-02-21 22:04:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
22页	480K
描述
1 K Ã 8 Dual-Port Static RAM

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中文翻译

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数据手册

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CY7C130_12 数据手册

CY7C130, CY7C130A

CY7C131, CY7C131A

1 K × 8 Dual-Port Static RAM

K × 8 Dual-Port Static RAM

Features

Functional Description

■ True dual-ported memory cells, which allow simultaneous

reads of the same memory location

The CY7C130/130A/CY7C131/131A/CY7C140^[1]and CY7C141

are high speed CMOS 1 K by 8 dual-port static RAMs. Two ports

are provided permitting independent access to any location in

memory. The CY7C130/130A/CY7C131/131A can be used as

either a standalone 8-bit dual-port static RAM or as a master

dual-port RAM in conjunction with the CY7C140/CY7C141 slave

dual-port device in systems requiring 16-bit or greater word

widths. It is the solution to applications requiring shared or

buffered data, such as cache memory for DSP, bit-slice, or multi-

processor designs.

■ 1 K × 8 organization

■ 0.65 micron CMOS for optimum speed and power

■ High speed access: 15 ns

■ Low operating power: I_CC= 110 mA (maximum)

■ Fully asynchronous operation

■ Automatic power-down

Each port has independent control pins; chip enable (CE), write

enable (R/W), and output enable (OE). Two flags are provided

on each port, BUSY and INT. BUSY signals that the port is trying

to access the same location currently being accessed by the

other port. INT is an interrupt flag indicating that data is placed

in a unique location (3FF for the left port and 3FE for the right

port). An automatic power down feature is controlled

independently on each port by the chip enable (CE) pins.

■ Master CY7C130/130A/CY7C131/131A easily expands data

bus width to 16 or more bits using slave CY7C140/CY7C141

■ BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY

input on CY7C140/CY7C141

■ INT flag for port-to-port communication

The CY7C130/130A and CY7C140 are available in 48-pin DIP.

The CY7C131/131A and CY7C141 are available in 52-pin

PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free

PQFP.

■ Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,

52-pin TQFP

■ Pb-free packages available

Logic Block Diagram

R/W

I/O

CONTROL

I/O

CONTROL

[2]

BUSY

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

ARBITRATION

LOGIC

(7C130/7C131 ONLY)

AND

INTERRUPT LOGIC

R/W

[3]

INT

Notes

1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.

2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.

CY7C140/CY7C141 (Slave): BUSY is input.

3. Open drain outputs: pull-up resistor required.

Cypress Semiconductor Corporation

Document Number: 38-06002 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 12, 2011

12 3 4 5 6 7...22

中文翻译

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与CY7C130_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C1300A	CYPRESS	获取价格	128K X 36 Dual I/O Dual Address Synchronous SRAM
CY7C1300A-100AC	CYPRESS	获取价格	128K X 36 Dual I/O Dual Address Synchronous SRAM
CY7C1300A-133AC	CYPRESS	获取价格	Dual-Port SRAM, 128KX36, 4ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
CY7C1300A-83AC	CYPRESS	获取价格	128K X 36 Dual I/O Dual Address Synchronous SRAM
CY7C1300A-83BGC	CYPRESS	获取价格	Dual-Port SRAM, 128KX36, 6ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
CY7C1301A	ETC	获取价格	Memory
CY7C1301A-100AC	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 5ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
CY7C1301A-133AC	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 4ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
CY7C1301A-83AC	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 6ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
CY7C1301A-83BGC	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 6ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176

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