Datasheet > CY7C1302BV25-200BZC

CY7C1302BV25-200BZC

更新时间： 2024-01-15 00:35:24

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
26页	412K
描述
QDR SRAM, 512KX18, 2.3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165

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CY7C1302BV25-200BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.89
Is Samacsys：	N	最长访问时间：	2.3 ns
其他特性：	PIPELINED ARCHITECTURE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	9437184 bit	内存集成电路类型：	QDR SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大供电电压 (Vsup)：	2.6 V	最小供电电压 (Vsup)：	2.4 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	13 mm
Base Number Matches：	1

CY7C1302BV25-200BZC 数据手册

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CY7C1302BV25

Preliminary

9 Mb Burst of 2 Pipelined SRAM with QDR Architecture

Features

Functional Description

• Separate Independent Read and Write Data Ports

—Supports concurrent transactions

• 167 MHz Clock for High Bandwidth

—2.5 ns Clock-to-Valid access time

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read &

Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

—SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mis-matches

• Single multiplexed address input bus latches address

inputs for both READ and WRITE ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

The CY7C1302BV25 is a 2.5V Synchronous Pipelined

SRAMs equipped with QDR architecture. QDR architecture

consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read

operations and the Write Port has dedicated Data inputs to

support Write operations. Access to each port is accomplished

through a common address bus. The Read address is latched

on the rising edge of the K clock and the Write address is

latched on the rising edge of K clock. QDR has separate data

inputs and data outputs to completely eliminate the need to

“turn-around” the data bus required with common I/O devices.

Accesses to the CY7C1302BV25 Read and Write ports are

completely independent of one another. All accesses are initi-

ated synchronously on the rising edge of the positive input

clock (K). In order to maximize data throughput, both Read

and Write ports are equipped with Double Data Rate (DDR)

interfaces. Therefore, data can be transferred into the device

on every rising edge of both input clocks (K and K) and out of

the device on every rising edge of the output clock (C and C)

thereby maximizing performance while simplifying system de-

sign. Each address location is associated with two 18-bit

words that burst sequentially into or out of the device.

• 13x15 mm 1.0 mm pitch fBGA package, 165 ball

(11x15 matrix) Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

Depth expansion is accomplished with a Port Select input for

each port. Each Port Selects allow each port to operate inde-

pendently.

• Variable Impedance HSTL

Configurations

CY7C1302BV25 – 512 Kb x 18

All synchronous inputs pass through input registers controlled

by the K orK input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are con-

ducted with on-chip synchronous self-timed write circuitry.

Logic Block Diagram (CY7C1302BV25)

D_[17:0]

Write

Data Reg

Address

(17:0)

Address

A_(17:0)

256Kx18 256Kx18

Memory Memory

Array

CLK

Gen.

RPS

Control

Logic

Read Data Reg.

Vref

Reg.

Control

Logic

WPS

BWS₀

Q_[17:0]

BWS₁

CypressSemiconductorCorporation

Document #: 38-05XXX Rev. **

•

3901NorthFirstStreet

•

SanJose

•

CA 95134

•

408-943-2600

Revised April 14, 2003

12 3 4 5 6 7...26

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与CY7C1302BV25-200BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1302CV25	CYPRESS	获取价格	9-Mbit Burst of Two Pipelined SRAMs with QDR⑩
CY7C1302CV25-100	CYPRESS	获取价格	9-Mbit Burst of Two Pipelined SRAMs with QDR⑩
CY7C1302CV25-100BZC	CYPRESS	获取价格	9-Mbit Burst of Two Pipelined SRAMs with QDR⑩
CY7C1302CV25-133	CYPRESS	获取价格	9-Mbit Burst of Two Pipelined SRAMs with QDR⑩
CY7C1302CV25-133BZC	CYPRESS	获取价格	9-Mbit Burst of Two Pipelined SRAMs with QDR⑩
CY7C1302CV25-167	CYPRESS	获取价格	9-Mbit Burst of Two Pipelined SRAMs with QDR⑩
CY7C1302CV25-167BZC	CYPRESS	获取价格	9-Mbit Burst of Two Pipelined SRAMs with QDR⑩
CY7C1302DV25	CYPRESS	获取价格	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture
CY7C1302DV25_06	CYPRESS	获取价格	9-Mbit Burst of Two Pipelined SRAMs with QDR⑩
CY7C1302DV25_11	CYPRESS	获取价格	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture JTAG Interface

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