Datasheet > CY7C1302V25

CY7C1302V25

更新时间： 2024-01-13 14:08:04

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
19页	384K
描述
Memory

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数据手册

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CY7C1302V25 数据手册

CY7C1302V25

9-Mb Pipelined SRAM with QDR™ Architecture

Features

Functional Description

• Separate independent read and write data ports

— Supports concurrent transactions

• 167-MHz clock for high bandwidth

— 2.5-ns clock-to-valid access time

• Two-word burst on all accesses

• Double data rate (DDR) interfaces on both read and

write ports (data transferred at 333 MHz) @ 167 MHz

• Two input clocks (K and K)^[1]for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) account for clock skew

and flight time mismatches

• Single multiplexed address input bus latches address

inputs for both read and write ports

• Separate port selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL inputs and outputs^[1]

The CY7C1302V25 is a 2.5V synchronous pipelined SRAM

with QDR™ architecture. QDR architecture consists of two

separate ports to access the memory array. The Read port has

dedicated Data Outputs to support Read operations and the

Write Port has dedicated Data inputs to support Write opera-

tions. Access to each port is accomplished through a common

address bus. The Read address is latched on the rising edge

of the K^[1]clock and the Write address is latched on the rising

edge of K^[1]clock. QDR has separate data inputs and data

outputs to completely eliminate the need to “turn-around” the

data bus required with common I/O devices. Accesses to the

CY7C1302V25 Read and Write ports are completely

independent of one another. All accesses are initiated

synchronously on the rising edge of the positive input clock

(K)^[1]. In order to maximize data throughput, both Read and

Write ports are equipped with DDR interfaces. Therefore, data

can be transferred into the device on every rising edge of both

input clocks (K and K)^[1]and out of the device on every rising

edge of the output clock (C and C) thereby maximizing perfor-

mance while simplifying system design.

• 13 × 15 mm – 1.0-mm pitch FBGA package, 165 ball

(11 × 15 matrix)

• Variable-drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG interface

Depth expansion is accomplished with Port Select inputs for

each port. This allows the ports to operate independently.

All synchronous inputs pass through input registers controlled

by the input clocks (K and K)^[1]. All data outputs pass through

output registers controlled by the output clocks (C or C). Writes

occur with on-chip synchronous self-timed write circuitry.

• Variable impedance HSTL

Logic Block Diagram

D_[17:0]

Write

Data Reg

Address

l17:0]

Address

A_[17:0]

256Kx18 256Kx18

Memory Memory

K^[1]

Array

CLK

Gen.

RPS

Control

Logic

Read Data Reg.

Vref

Reg.

Control

Logic

WPS

BWS₀

Q_[17:0]

BWS₁

Note:

1. K and K inputs require V_IHto be greater than V_REF+ 0.5V and V_ILto be less than V_REF– 0.5V. This is a subset of JEDEC standards for HSTL I/Os.

Cypress Semiconductor Corporation

Document #: 38-05260 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised November 12, 2002

12 3 4 5 6 7...19

中文翻译

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与CY7C1302V25相关器件

型号	品牌	获取价格	描述	数据表
CY7C130-30DC	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 30ns, CMOS, CDIP48, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-48
CY7C130-30DI	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 30ns, CMOS, CDIP48, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-48
CY7C130-30LC	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 30ns, CMOS, CQCC48, CERAMIC, LCC-48
CY7C130-30PC	CYPRESS	获取价格	1K x 8 Dual-Port Static Ram
CY7C130-30PI	CYPRESS	获取价格	1K x 8 Dual-Port Static Ram
CY7C130-30PV	ETC	获取价格	IC-1KX8 DUAL PORT RAM
CY7C130-35DC	ETC	获取价格	x8 Dual-Port SRAM
CY7C130-35DI	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 35ns, CMOS, CDIP48, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-48
CY7C130-35DMB	CYPRESS	获取价格	1K x 8 Dual-Port Static Ram
CY7C130-35FMB	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 35ns, CMOS, CQFP48, CERAMIC, QFP-48

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