Datasheet > 存储 > SRAM> CY7C1303AV18-100BZC

CY7C1303AV18-100BZC

更新时间： 2024-01-15 05:16:01

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储静态存储器
页数	文件大小	规格书
20页	481K
描述
18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Architecture

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技术参数
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CY7C1303AV18-100BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.88
Is Samacsys：	N	Base Number Matches：	1

CY7C1303AV18-100BZC 数据手册

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CY7C1303AV18

CY7C1306AV18

PRELIMINARY

18-MbBurstof2PipelinedSRAMwithQDR™Architecture

Features

Functional Description

• Separate independent Read and Write data ports

The CY7C1303AV18 and CY7C1306AV18 are 1.8V

Synchronous Pipelined SRAMs equipped with QDR™ archi-

tecture. QDR architecture consists of two separate ports to

access the memory array. The Read port has dedicated Data

Outputs to support Read operations and the Write Port has

dedicated Data inputs to support Write operations. Access to

each port is accomplished through a common address bus.

The Read address is latched on the rising edge of the K clock

and the Write address is latched on the rising edge of K clock.

QDR has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus required with

common I/O devices. Accesses to the CY7C1303AV18/

CY7C1306AV18 Read and Write ports are completely

independent of one another. All accesses are initiated

synchronously on the rising edge of the positive input clock

(K). In order to maximize data throughput, both Read and

Write ports are equipped with Double Data Rate (DDR) inter-

faces. Therefore, data can be transferred into the device on

every rising edge of both input clocks (K and K) and out of the

device on every rising edge of the output clock (C and C, or K

and K when in single clock mode) thereby maximizing perfor-

mance while simplifying system design. Each address location

is associated with two 18-bit words (CY7C1303AV18) or two

36-bit words (CY7C1306AV18) that burst sequentially into or

out of the device.

— Supports concurrent transactions

• 167-MHz Clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) account for clock skew

and flight time mismatching

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL Inputs and Outputs

• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball

(11x15 matrix)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

Depth expansion is accomplished with a Port Select input for

each port. Each Port Selects allow each port to operate

independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

• Variable Impedance HSTL

Configurations

CY7C1303AV18 – 1M x 18

CY7C1306AV18 – 512K x 36

Logic Block Diagram (CY7C1303AV18)

D_[17:0]

Write

Data Reg

Address

(18:0)

Address

A_(18:0)

512Kx18 512Kx18

Memory Memory

Array

CLK

Gen.

RPS

Control

Logic

Read Data Reg.

Vref

Reg.

Control

Logic

WPS

BWS₀

Q_[17:0]

BWS₁

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05492 Rev. *A

Revised June 1, 2004

12 3 4 5 6 7...20

中文翻译

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与CY7C1303AV18-100BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1303AV18-133BZC	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1303AV18-167BZC	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1303AV25	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1303AV25-100BZC	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1303AV25-133BZC	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1303AV25-167BZC	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1303BV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C1303BV18-100BZC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A
CY7C1303BV18-133BZC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A
CY7C1303BV18-167BZC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A

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