Datasheet > CY7C1301A

CY7C1301A

更新时间： 2024-02-17 21:46:22

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
13页	148K
描述
Memory

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数据手册

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CY7C1301A 数据手册

CY7C1301A

256K X 36 Dual I/O, Dual Address Synchronous SRAM

The CY7C1301A allows the user to concurrently perform

reads, writes, or pass-through cycles in combination on the

two data ports. The two address ports (AX, AY) determine the

read or write locations for their respective data ports (DQX,

DQY).

Features

• Fast Clock Speed: 100 and 83 MHz

• Fast Access Times: 5.0/6.0 ns Max.

• Single Clock Operation

All input pins except Output Enable pins (OEX, OEY) are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, depth-expansion Chip Enables

(CE1X, CE2X, CE1Y and CE2Y), Pass-Through controls (PTX

and PTY), and Read-Write control (WEX and WEY).

• Single 3.3V –5% and +5% power supply VCC

• Separate V_CCQfor output buffer

• Two Chip Enables for simple depth expansion

• Address, Data Input, CE1X, CE2X, CE1Y, CE2Y, PTX,

PTY, WEX, WEY, and Data Output Registers On-Chip

• Concurrent Reads and Writes

• Two bidirectional Data Buses

• Can be configured as separate I/O

• Pass-Through feature

• Asynchronous Output Enables (OEX, OEY)

• LVTTL-Compatible I/O

• Self-Timed write

• Automatic power-down

• 176-Pin TQFP Package

The pass-through feature allows data to be passed from one

port to the other, in either direction. The PTX input must be

asserted to pass data from port X to port Y. The PTY will

likewise pass data from port Y to port X. A pass-through

operation takes precedence over a read operation.

For the case when AX and AY are the same, certain protocols

are followed. If both ports are read, the reads occur normally.

If one port is written and the other is read, the read from the

array will occur before the data is written. If both ports are

written, only the data on DQY will be written to the array.

The CY7C1301A operates from a +3.3V power supply. All

inputs and outputs are LVTTL-compatible. These dual I/O,

dual address synchronous SRAMs are well suited for ATM,

Ethernet switches, routers, cell/frame buffers, SNA switches

and shared memory applications.

Functional Description

The CY7C1301A SRAM integrates 262,144 x 36 SRAM cells

with advanced synchronous peripheral circuitry. It employs

high-speed, low-power CMOS designs using advanced

triple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The CY7C1301A device needs one extra cycle after power for

proper power on reset. The extra cycle is needed after V_CCis

stable on the device. This device is available in a 176-pin

TQFP package.

Logic Block Diagram^[1]

18/17

*AX

18/17

AY*

Address

256K/128K x 9 x 4

SRAM Array

WEX#

PTX#

WEY#

PTY#

Write X

Write

Driver

Sensing

Amplifiers

Sensing

Amplifiers

Write

Driver

Write Y

PTX

Pass-Through

Data In

Output

Data In

CLK

CE1X#

CE2X

CE1Y#

CE2Y

DQX

DQY

Chip Enable

OEX#

OEY#

Note:

1. For 256 × 36 device, AX and AY are 18-bit-wide buses.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document # 38-05076 Rev. *C

Revised January 19, 2003

12 3 4 5 6 7...13

中文翻译

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与CY7C1301A相关器件

型号	品牌	获取价格	描述	数据表
CY7C1301A-100AC	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 5ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
CY7C1301A-133AC	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 4ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
CY7C1301A-83AC	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 6ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
CY7C1301A-83BGC	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 6ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
CY7C130-25DC	ETC	获取价格	x8 Dual-Port SRAM
CY7C130-25LC	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 25ns, CMOS, CQCC48, CERAMIC, LCC-48
CY7C130-25PC	ETC	获取价格	x8 Dual-Port SRAM
CY7C1302BV25-133BZC	CYPRESS	获取价格	QDR SRAM, 512KX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C1302BV25-200BZC	CYPRESS	获取价格	QDR SRAM, 512KX18, 2.3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C1302CV25	CYPRESS	获取价格	9-Mbit Burst of Two Pipelined SRAMs with QDR⑩

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