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CY7C1302BV25
Preliminary
9 Mb Burst of 2 Pipelined SRAM with QDR Architecture
Features
Functional Description
• Separate Independent Read and Write Data Ports
—Supports concurrent transactions
• 167 MHz Clock for High Bandwidth
—2.5 ns Clock-to-Valid access time
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read &
Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
—SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mis-matches
• Single multiplexed address input bus latches address
inputs for both READ and WRITE ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
The CY7C1302BV25 is a 2.5V Synchronous Pipelined
SRAMs equipped with QDR architecture. QDR architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write Port has dedicated Data inputs to
support Write operations. Access to each port is accomplished
through a common address bus. The Read address is latched
on the rising edge of the K clock and the Write address is
latched on the rising edge of K clock. QDR has separate data
inputs and data outputs to completely eliminate the need to
“turn-around” the data bus required with common I/O devices.
Accesses to the CY7C1302BV25 Read and Write ports are
completely independent of one another. All accesses are initi-
ated synchronously on the rising edge of the positive input
clock (K). In order to maximize data throughput, both Read
and Write ports are equipped with Double Data Rate (DDR)
interfaces. Therefore, data can be transferred into the device
on every rising edge of both input clocks (K and K) and out of
the device on every rising edge of the output clock (C and C)
thereby maximizing performance while simplifying system de-
sign. Each address location is associated with two 18-bit
words that burst sequentially into or out of the device.
• 13x15 mm 1.0 mm pitch fBGA package, 165 ball
(11x15 matrix) Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
Depth expansion is accomplished with a Port Select input for
each port. Each Port Selects allow each port to operate inde-
pendently.
• Variable Impedance HSTL
Configurations
CY7C1302BV25 – 512 Kb x 18
All synchronous inputs pass through input registers controlled
by the K orK input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1302BV25)
D[17:0]
18
Write
Write
Data Reg
Data Reg
Address
Register
A
(17:0)
Address
Register
A(17:0)
18
18
256Kx18 256Kx18
Memory Memory
Array
Array
K
CLK
Gen.
RPS
Control
Logic
K
C
C
Read Data Reg.
36
18
Vref
18
Reg.
Reg.
Reg.
18
18
Control
Logic
WPS
BWS0
18
Q[17:0]
BWS1
CypressSemiconductorCorporation
Document #: 38-05XXX Rev. **
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3901NorthFirstStreet
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SanJose
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CA 95134
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408-943-2600
Revised April 14, 2003