Datasheet > CY7C1298H

CY7C1298H

更新时间： 2024-10-01 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
16页	381K
描述
1-Mbit (64K x 18) Pipelined DCD Sync SRAM

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CY7C1298H 数据手册

CY7C1298H

1-Mbit (64K x 18) Pipelined DCD Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

— Depth expansion without wait state

The CY7C1298H SRAM integrates 64K x 18 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW_[A:B], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

• 64K × 18-bit common I/O architecture

• 3.3V core power supply (V_DD

)

• 2.5V/3.3V I/O power supply (V_DDQ

)

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

controlled by the byte write control inputs. GW active LOW

causes all bytes to be written. This device incorporates an

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• Asynchronous Output Enable

• Available in JEDEC-standard lead-free 100-Pin TQFP

package

• “ZZ” Sleep Mode option

The CY7C1298H operates from a +3.3V core power supply

while all outputs operate either with a +2.5V or +3.3V supply.

All

inputs

and

outputs

are

JEDEC-standard

JESD8-5-compatible.

Selection Guide

166 MHz

3.5

133 MHz

4.0

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

240

225

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05665 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 5, 2006

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与CY7C1298H相关器件

型号	品牌	获取价格	描述	数据表
CY7C1298H-100AXC	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H-100AXI	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H-133AXC	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H-133AXI	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1299A	CYPRESS	获取价格	32K x 36 Dual I/O Dual Address Synchronous SRAM
CY7C1299A-100AC	CYPRESS	获取价格	32K x 36 Dual I/O Dual Address Synchronous SRAM
CY7C1299A-83AC	CYPRESS	获取价格	32K x 36 Dual I/O Dual Address Synchronous SRAM
CY7C129DV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C129EV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C130	CYPRESS	获取价格	1K x 8 Dual-Port Static Ram

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